// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1ns / 1ps
`include "mainfpga_version.vh"

module beechnut_city_main
  #(parameter FPGA_REV = 8'h00, FPGA_REV_TEST = 8'h00)
   (
    //Input CLK
    input  iClk_2M,
    input  iClk_20M,
	input  iClk_50M,
    input  iClk_100M,
    input  iRST_N,

    input iLTPI_LINK_ALIGNED,
    
    //PLT AUX RAIL
    input  PWRGD_P3V3_AUX,
    input  PWRGD_P1V8_AUX,
    input  PWRGD_P5V_AUX,
    
    //SYS_CHECK
    input  FM_CPU1_SKTOCC_LVT3_PLD_N,
    input  FM_CPU0_SKTOCC_LVT3_PLD_N,
    input  FM_CPU0_PROC_ID1,
    input  FM_CPU0_PROC_ID0,
    input  FM_CPU1_PROC_ID1,
    input  FM_CPU1_PROC_ID0,
    input  FM_CPU0_PKGID2,
    input  FM_CPU0_PKGID1,
    input  FM_CPU0_PKGID0,
    input  FM_CPU1_PKGID2,
    input  FM_CPU1_PKGID1,
    input  FM_CPU1_PKGID0,
    output   oCPU_MISMATCH,
    
    //CPU AUX

    input  iCpu1IntrClkConfDone,
    
    input  iAUX_PWRGD_CPU0_SCM, //from SCM FPGA thru LVDS
    input  iAUX_PWRGD_CPU1_SCM, //from SCM FPGA thru LVDS
    input  iIBL_RDY_N, //from DBG PLD thru sGPIO
    input  iFM_CPU0_INTR_PRSNT_N, //from DBG PLD thru sGPIO
    input  iFM_CPU1_INTR_PRSNT_N, //from DBG PLD thru sGPIO

    output oCPU1_AUX_PWR_OK,
    output oCPU_AUX_PWR_FLT, ////To DBG FPGA via sGPIO
    
    output oCPU0_AUX_PWR_OK,
    //VR BYPASS
    input  iFM_FORCE_PWRON_LVC18, //Coming from DBG FPGA via sGPIO
    output [7:0] oLED_STATUS,
    
    //DC-SCM
    input  iBMC_ONCTL_N, //from SCM FPGA thru LVDS
    input  iSCM_BMC_Done, //from SCM FPGA thru LVDS
    input  iSCM_BMC_FLT, //from SCM FPGA thru LVDS
    
    
    //PSU CONTROL
    input  FM_S5_WITH_12V_N,
    input  PWRGD_PS_PWROK_CPU_PLD_R,
    input  PWRGD_P3V3,
    output oFM_PLD_CLKS_DEV_R_EN,
    output oPSU_FAULT,
    output oP3V3_FAULT,

    input  iSURPRISE_RESET,
    input  iFM_GLOBAL_RESET,
    
    output [2:0] oPSU_FLT_CODE, //To DBG FPGA via sGPIO
    
    //VR ENABLE
    output FM_P3V3_EN, 
    output FM_PS_EN_R, 
    output FM_AUX_SW_EN, 
    output FM_P5V_EN,
    output FM_P1V0_AUX_EN,
    output FM_P1V1_AUX_EN, 
    
    output FM_P12V_DIMM_PCIE_SW_CPU0_EN, 
    output FM_P12V_DIMM_PCIE_SW_CPU1_EN,
    
    //CPU ERROR CODe
    output [7:0] oCPU0_FLT_CODE, //To DBG FPGA via sGPIO
    output [7:0] oCPU1_FLT_CODE, //To DBG FPGA via sGPIO
    
    //MEM ERROR CODe
    output [5:0] oCPU0_DIMM_FLT_CODE, //To DBG FPGA via sGPIO
    output [5:0] oCPU1_DIMM_FLT_CODE, //To DBG FPGA via sGPIO
    
    //CPU0 VR enable
    output   FM_PVCCFA_EHV_CPU0_R_EN, 
    output   FM_PVNN_MAIN_CPU0_R_EN, 
    output   FM_PVCCD_HV_CPU0_R_EN,
    
    output   FM_PVCCFA_EHV_FIVRA_CPU0_R_EN, 
    output   FM_PVCCINFAON_CPU0_R_EN, 
    output   FM_PVCCIN_CPU0_R_EN, 
    
    //CPU1 VR enable
    output   FM_PVCC3V3_AUX_CPU1_EN, 
    
    output   FM_PVCCFA_EHV_CPU1_R_EN, 
    output   FM_PVNN_MAIN_CPU1_R_EN, 
    output   FM_PVCCD_HV_CPU1_R_EN, 
    
    output   FM_PVCCFA_EHV_FIVRA_CPU1_R_EN, 
    output   FM_PVCCINFAON_CPU1_R_EN, 
    output   FM_PVCCIN_CPU1_R_EN,
    
    //AUX
    input  iPWRGD_P1V0_AUX,
    input  iPWRGD_P1V1_AUX,
    
    //CPU
    input  FM_SLPS3_CPU0_CPU_PLD_N,
    input  FM_SLPS4_CPU0_CPU_PLD_N,
    input  FM_SLPS3_CPU1_CPU_PLD_N,
    input  FM_SLPS4_CPU1_CPU_PLD_N,

    input  PWRGD_PVCCFA_EHV_CPU0,
    input  PWRGD_PVNN_MAIN_CPU0,
    input  PWRGD_PVCCD0_HV_CPU0,
    input  PWRGD_PVCCD1_HV_CPU0,
    
    input  PWRGD_PVCCFA_EHV_FIVRA_CPU0,
    input  PWRGD_PVCCINFAON_CPU0,
    input  PWRGD_PVCCIN_CPU0,
    input  FM_CPU0_GLB_RST_WARN_PLD_N,
    input  PWRGD_PVCCFA_EHV_CPU1,
    input  PWRGD_PVNN_MAIN_CPU1,
    input  PWRGD_PVCCD0_HV_CPU1,
    input  PWRGD_PVCCD1_HV_CPU1,
    
    input  PWRGD_PVCCFA_EHV_FIVRA_CPU1,
    input  PWRGD_PVCCINFAON_CPU1,
    input  PWRGD_PVCCIN_CPU1,
    input  FM_CPU1_GLB_RST_WARN_PLD_N,
    input  FM_CPU0_REFCLK_RDY_PLD,
    input  FM_CPU1_REFCLK_RDY_PLD,
    input  iRST_PLTRST_CPU0_PFR_LVC3_N, //PLTRST coming from PFR thru LVDS
    input  iRST_PLTRST_CPU1_PFR_LVC3_N, //PLTRST coming from PFR thru LVDS
    
    
    output   PWRGD_AUX_PWRGD_CPU0_PLD,
    output   PWRGD_AUX_PWRGD_CPU1_PLD,
    output   PWRGD_S0_PWROK_CPU0_R,
    output   PWRGD_S0_PWROK_CPU1_R,
    output   PWRGD_CPU0_LVC1_R,
    output   PWRGD_CPU1_LVC1_R,
    output   FM_S5_PWR_RETAINED_CPU0_PLD,
    output   RST_CPU0_RESET_R_N,
    output   RST_CPU1_RESET_R_N,
    
    //MEM
    input  M_AB_CPU0_RESET_N, 
    input  M_CD_CPU0_RESET_N,
    input  M_EF_CPU0_RESET_N,
    input  M_GH_CPU0_RESET_N,
    
    input  M_AB_CPU1_RESET_N, 
    input  M_CD_CPU1_RESET_N,
    input  M_EF_CPU1_RESET_N,
    input  M_GH_CPU1_RESET_N,
    
    inout  PWRGD_FAIL_CPU0_AB_PLD,
    inout  PWRGD_FAIL_CPU0_CD_PLD,
    inout  PWRGD_FAIL_CPU0_EF_PLD,
    inout  PWRGD_FAIL_CPU0_GH_PLD,
    
    inout  PWRGD_FAIL_CPU1_AB_PLD,
    inout  PWRGD_FAIL_CPU1_CD_PLD,
    inout  PWRGD_FAIL_CPU1_EF_PLD,
    inout  PWRGD_FAIL_CPU1_GH_PLD,
    
    output   PWRGD_DRAMPWRGD_CPU0_AB_R_LVC1,
    output   PWRGD_DRAMPWRGD_CPU0_CD_R_LVC1,
    output   PWRGD_DRAMPWRGD_CPU0_EF_R_LVC1,
    output   PWRGD_DRAMPWRGD_CPU0_GH_R_LVC1,
    
    output   PWRGD_DRAMPWRGD_CPU1_AB_R_LVC1,
    output   PWRGD_DRAMPWRGD_CPU1_CD_R_LVC1,
    output   PWRGD_DRAMPWRGD_CPU1_EF_R_LVC1,
    output   PWRGD_DRAMPWRGD_CPU1_GH_R_LVC1,
    
    output   M_AB_CPU0_FPGA_RESET_R_N,
    output   M_CD_CPU0_FPGA_RESET_R_N,
    output   M_EF_CPU0_FPGA_RESET_R_N,
    output   M_GH_CPU0_FPGA_RESET_R_N,
    
    output   M_AB_CPU1_FPGA_RESET_R_N,
    output   M_CD_CPU1_FPGA_RESET_R_N,
    output   M_EF_CPU1_FPGA_RESET_R_N,
    output   M_GH_CPU1_FPGA_RESET_R_N,
    
    //PLT LOGic
    input  FM_RST_PERST_BIT0,
    input  FM_RST_PERST_BIT1,
    input  FM_RST_PERST_BIT3,
    input  FM_PASSWORD_CLEAR_N,
    input  FM_POSTCODE_PFR_CC_SEL_N,
    input  IRQ_PMBUS_PLD_ALERT_N,

    input    FM_SERIAL_BOOT,
    input    FM_PERST_TIMING_SEL,
    
    output   RST_PLD_PCIE_CPU0_DEV_PERST_R_N,
    output   RST_PLD_PCIE_CPU1_DEV_PERST_R_N,
    
    output   H_CPU0_PROCHOT_LVC1_R_N,
    output   H_CPU1_PROCHOT_LVC1_R_N,
    output   H_CPU0_MEMHOT_IN_LVC1_R_N,
    output   H_CPU1_MEMHOT_IN_LVC1_R_N,
    output   FM_SYS_THROTTLE_R_N,
    
    
    //ERROR
    input  IRQ_CPU0_VRHOT_N,
    input  IRQ_CPU1_VRHOT_N,
    input  IRQ_CPU0_MEM_VRHOT_N,
    input  IRQ_CPU1_MEM_VRHOT_N,
    input  H_CPU0_CATERR_LVC1_N,
    input  H_CPU0_RMCA_LVC1_N,
    input  H_CPU1_CATERR_LVC1_N,
    input  H_CPU1_RMCA_LVC1_N,
    output [1:0] oH_CPU0_CATERR_LVC1_ENCODE,
    output [1:0] oH_CPU0_RMCA_LVC1_ENCODE,
    output [1:0] oH_CPU1_CATERR_LVC1_ENCODE,
    output [1:0] oH_CPU1_RMCA_LVC1_ENCODE,
    
    //OCP NIC
    input  PWRGD_OCP0_PWR,
    input  FM_OCP0_CARD_PRSNTB_LVC3_N,
    output   o_FM_OCP_AUX_PWR_EN,
    output   o_FM_OCP_MAIN_PWR_EN,
    output   o_FM_PLD_OCP_RBT_ISOLATE_N,
    output   o_OcpPwrFlt_LED, 
    
    //EDSFF CARD
    inout  FM_M2_EDSFF_PRSNT_N,
    inout  FM_SFFX4_EXPCARD_IO_B_0 ,
    
    
    //DC-SCM SPEC
    input  FM_HPM_STBY_EN,
    input  FM_HPM_STBY_RST_N,
    output oFM_HPM_STBY_RDY,
    input  FM_SCM_PRSNT0_LVC3_N,
    
    //ADR
    input  FM_ADR_MODE0,
    input  FM_ADR_MODE1,
    input  FM_CPU0_ADR_TRIGGER_N,     //ADR_TRIGGER input from CPU
    input  FM_CPU0_ADR_EXT_TRIGGER_N,
    input  FM_CPU1_ADR_EXT_TRIGGER_N,
    input  FM_ADR_COMPLETE_PLD,
    input  FM_ADR_COMPLETE_P1_PLD,
    output oFM_CPU0_ADR_TRIGGER_N,    //ADR_TRIGGER output to CPU
	  output [31:0]  ADRcounter1,
	  output [31:0]  ADRcounter2,
    
    
    //Signals directly to LVDS, GlitchFilter'ed inside this module
    //CPU0 VNN 
    input  H_CPU0_THERMTRIP_LVC1_N, //to SCM FPGA thru LVDS   
    input  H_CPU0_MEMTRIP_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU0_MEMHOT_OUT_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU0_ERR0_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU0_ERR1_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU0_ERR2_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU0_MON_FAIL_PLD_LVC1_N, //to SCM FPGA thru LVDS
    
    output   oH_CPU0_THERMTRIP_LVC1_N, //to SCM FPGA thru LVDS   
    output   oH_CPU0_MEMTRIP_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU0_MEMHOT_OUT_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU0_ERR0_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU0_ERR1_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU0_ERR2_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU0_MON_FAIL_PLD_LVC1_N, //to SCM FPGA thru LVDS
    
    //CPU1 VNN
    input  H_CPU1_THERMTRIP_LVC1_N, //to SCM FPGA thru LVDS   
    input  H_CPU1_MEMTRIP_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU1_MEMHOT_OUT_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU1_ERR0_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU1_ERR1_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU1_ERR2_LVC1_N, //to SCM FPGA thru LVDS
    input  H_CPU1_MON_FAIL_PLD_LVC1_N, //to SCM FPGA thru LVDS
    
    output   oH_CPU1_THERMTRIP_LVC1_N, //to SCM FPGA thru LVDS   
    output   oH_CPU1_MEMTRIP_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU1_MEMHOT_OUT_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU1_ERR0_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU1_ERR1_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU1_ERR2_LVC1_N, //to SCM FPGA thru LVDS
    output   oH_CPU1_MON_FAIL_PLD_LVC1_N, //to SCM FPGA thru LVDS
    
    //PLT LOGic
    input  FP_PWR_BTN_N, //to SCM FPGA thru LVDS
    
    input  FM_SMB_BMC_NVME_LVC3_ALERT_N, //to SCM FPGA thru LVDS
    input  FM_BOARD_SKU_ID0, //to SCM FPGA thru LVDS
    input  FM_BOARD_SKU_ID1, //to SCM FPGA thru LVDS
    input  FM_BOARD_SKU_ID2, //to SCM FPGA thru LVDS
    input  FM_BOARD_SKU_ID3, //to SCM FPGA thru LVDS
    input  FM_BOARD_SKU_ID4, //to SCM FPGA thru LVDS
    input  FM_BOARD_REV_ID0, //to SCM FPGA thru LVDS
    input  FM_BOARD_REV_ID1, //to SCM FPGA thru LVDS
    input  FM_BOARD_REV_ID2, //to SCM FPGA thru LVDS
    input  FM_STANDALONE_MODE_N, //to SCM FPGA thru LVDS
    input  FM_4S_8S_MODE_N, //to SCM FPGA thru LVDS
    input  FM_NODE_ID0, //to SCM FPGA thru LVDS
    input  FM_NODE_ID1, //to SCM FPGA thru LVDS
    input  FM_S3M_CPU0_CPLD_CRC_ERROR, //to SCM FPGA thru LVDS
    input  FM_S3M_CPU1_CPLD_CRC_ERROR, //to SCM FPGA thru LVDS
    input  FM_1200VA_OC, //to SCM FPGA thru LVDS
    input  FM_BMC_SAFS_SEL, //to SCM FPGA thru LVDS
    input  iFM_DUAL_PARTITION_N, //to SCM FPGA thru LVDS
    input  iFM_PARTITION_SEL, //to SCM FPGA thru LVDS  

    output   oFM_SMB_BMC_NVME_LVC3_ALERT_N, //to SCM FPGA thru LVDS
    output   oFM_BOARD_SKU_ID0, //to SCM FPGA thru LVDS
    output   oFM_BOARD_SKU_ID1, //to SCM FPGA thru LVDS
    output   oFM_BOARD_SKU_ID2, //to SCM FPGA thru LVDS
    output   oFM_BOARD_SKU_ID3, //to SCM FPGA thru LVDS
    output   oFM_BOARD_SKU_ID4, //to SCM FPGA thru LVDS
    output   oFM_BOARD_REV_ID0, //to SCM FPGA thru LVDS
    output   oFM_BOARD_REV_ID1, //to SCM FPGA thru LVDS
    output   oFM_BOARD_REV_ID2, //to SCM FPGA thru LVDS
    output   oFM_STANDALONE_MODE_N, //to SCM FPGA thru LVDS
    output   oFM_4S_8S_MODE_N, //to SCM FPGA thru LVDS
    output   oFM_NODE_ID0, //to SCM FPGA thru LVDS
    output   oFM_NODE_ID1, //to SCM FPGA thru LVDS
    output   oFM_S3M_CPU0_CPLD_CRC_ERROR, //to SCM FPGA thru LVDS
    output   oFM_S3M_CPU1_CPLD_CRC_ERROR, //to SCM FPGA thru LVDS
    output   oFM_1200VA_OC, //to SCM FPGA thru LVDS
    output   oFM_BMC_SAFS_SEL, //to SCM FPGA thru LVDS
    
    //Signals both used in this module and tunnel to LVDS/SGPIO, GlitchFilter'ed inside this module
    output   oIRQ_CPU0_VRHOT_N, //to SCM FPGA thru LVDS
    output   oIRQ_CPU1_VRHOT_N, //to SCM FPGA thru LVDS
    output   oIRQ_CPU0_MEM_VRHOT_N, //to SCM FPGA thru LVDS
    output   oIRQ_CPU1_MEM_VRHOT_N, //to SCM FPGA thru LVDS
    output   oFM_CPU1_SKTOCC_LVT3_PLD_N, //to SCM FPGA thru LVDS
    output   oFM_CPU0_SKTOCC_LVT3_PLD_N, //to SCM FPGA thru LVDS
    output   oFM_CPU0_PROC_ID1, //to SCM FPGA thru LVDS
    output   oFM_CPU0_PROC_ID0, //to SCM FPGA thru LVDS
    output   oFM_CPU1_PROC_ID1, //to SCM FPGA thru LVDS
    output   oFM_CPU1_PROC_ID0, //to SCM FPGA thru LVDS
    output   oFM_CPU0_PKGID2, //to SCM FPGA thru LVDS
    output   oFM_CPU0_PKGID1, //to SCM FPGA thru LVDS
    output   oFM_CPU0_PKGID0, //to SCM FPGA thru LVDS
    output   oFM_CPU1_PKGID2, //to SCM FPGA thru LVDS
    output   oFM_CPU1_PKGID1, //to SCM FPGA thru LVDS
    output   oFM_CPU1_PKGID0, //to SCM FPGA thru LVDS
    output   oPWRGD_PS_PWROK_CPU_PLD_R, //to SCM FPGA thru LVDS
    output   oFM_SLPS4_CPU0_CPU_PLD_N, //to SCM FPGA thru LVDS
    output   oFM_SLPS3_CPU0_CPU_PLD_N, //to SCM FPGA thru LVDS
    output   oFM_SLPS4_CPU1_CPU_PLD_N, //to SCM FPGA thru LVDS
    output   oFM_SLPS3_CPU1_CPU_PLD_N, //to SCM FPGA thru LVDS
    output   oIRQ_PMBUS_PLD_ALERT_N, //to SCM FPGA thru LVDS
    output   oPWRGD_CPU0_LVC1_R, //to SCM FPGA thru LVDS
    output   oMEM_PWR_FLT,
    output   oCPU_PWR_FLT,
    output   oFM_POSTCODE_PFR_CC_SEL_N,

    output   oPWRGD_PVNN_MAIN_CPU0_FF,  //sync'ed version
    output   oPWRGD_PVNN_MAIN_CPU1_FF,  //sync'ed version
    
    output   oHeartBeat,
    
    //Signals both used in this module and tunnel to LVDS, GlitchFilter'ed inside this module
    output [3:0] oMasterCode,
    output [3:0] pwr_err_source,
    input        pwr_restart,
    input        force_to_enter_err,
    output       force_to_enter_err_clear,
    output       pwr_restart_clear,
    
    //SMBUS For PCA9555
    inout  SMB_PCIE_STBY_LVC3_SCL,
    inout  SMB_PCIE_STBY_LVC3_SDA,
    inout  SMB_PEHPCPU0_LVC3_FPGA_SCL,
    inout  SMB_PEHPCPU0_LVC3_FPGA_SDA,
    inout  FM_FAULT_LED_AMBER_M2_EDSFF_N,
    inout  FM_PWRDIS_EDSFF,

    output  oCpu0IntrPrsnt_n,
    output  oCpu1IntrPrsnt_n,
    output  oCpu0IntrTypeABn,
    output  oCpu1IntrTypeABn,
	
	input   iLegacyNode,
	
	input   iwInModular,
	input   iwInRP,
	input   PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3,
    output  RST_PLD_PCIE_CPU0_x16_PERST,
    output  RST_PLD_PCIE_CPU0_DCSCM_PERST,
	
	    input             iGLBRST_HOLD_OFF,

    output [2:0] CurrentTime_Masterfub,

    input rjo_ready,
    input rjo_ready_sec,
	
    input  iCPU0_PWRBTN_FPGA_N,
	input  iCPU0_RSTBTN_FPGA_N,
	
	output oFM_THERMTRIP_CPU0_LED_LATCHED,
	output oFM_THERMTRIP_CPU1_LED_LATCHED,
	
	//MBVR flow
	output  oMBVR_ready_sync,
    input   iMBVR_ready_ack
    );
   
   //////////////////////////////////////////////////////////////////////////////////
     // Parameters
   //////////////////////////////////////////////////////////////////////////////////
   
   localparam  LOW =1'b0;
   localparam  HIGH=1'b1;

   localparam  MAIN2MODREGS = 20;
   
   //////////////////////////////////////////////////////////////////
   //Internal signals
   //////////////////////////////////////////////////////////////////
   
   //SYS_CHECK
   wire                         wSYS_OK;
   wire                         wCpu0IntrPrsnt_n;
   wire                         wCpu1IntrPrsnt_n;
   wire                         wSOCKET_REMOVED;
   
   //MASTER SEQ
   wire                         wHBM_EN;

   //CPU AUX
   wire                         wCPU0_AUX_EN;
   wire                         wCPU1_AUX_EN;
   wire                         wCPU0_AUX_PWR_OK;
   wire                         wCPU1_AUX_PWR_OK;
   wire                         wCPU0_AUX_PWR_FLT;
   wire                         wCPU1_AUX_PWR_FLT;
   wire                         wPWRGD_AUX_PWRGD_CPU0;
   wire                         wPWRGD_AUX_PWRGD_CPU1;
   wire                         wAUX_PWRGD_CPU0_SCM;
   wire                         wAUX_PWRGD_CPU1_SCM;
   wire                         PWRGD_AUX_PWRGD_CPU0_PLD_NEGEDGE;
   wire                         PWRGD_AUX_PWRGD_CPU0_PLD_POSEDGE;
   wire                         wAUX_PWRGD_CPU0_SCM_NEGEDEG;
   wire                         wFM_S5_PWR_RETAINED;
   reg                          rAUX_PWRGD_CPU0_SCM_NEGEDEG_LATCHED;
   wire                         wAUX_VR_PWROFF_CPU0_ERR;
   wire                         wAUX_VR_PWROFF_CPU1_ERR;
   wire                         wAUX_VR_PWROFF_ERR;
   wire                         wVR_PWROFF_CPU0_ERR;
   wire                         wVR_PWROFF_CPU1_ERR;
   wire                         wVR_PWROFF_ERR;
   
   //PSU
   wire                         wPSU_EN;
   wire                         wFM_PS_EN_R;
   wire                         wFM_P5V_EN;
   wire                         wFM_P3V3_EN;
   wire                         wFM_AUX_SW_EN;
   wire                         wFM_P12V_DIMM_PCIE_SW_CPU0_EN;
   wire                         wFM_P12V_DIMM_PCIE_SW_CPU1_EN;
   wire                         wPSU_PWR_OK;
   wire                         wPSU_PWR_FLT;
   
   //CPU Main
   wire                         wFM_P1V0_AUX_EN, wFM_P1V0_AUX_CPU0_EN, wFM_P1V1_AUX_CPU0_EN, wFM_P1V0_AUX_CPU1_EN, wFM_P1V1_AUX_CPU1_EN;
   

   wire                         wFM_P1V0_AUX_CPU0_EN_SPR, wFM_P1V0_AUX_CPU1_EN_SPR, wFM_P1V0_AUX_CPU0_EN_GNR, wFM_P1V0_AUX_CPU1_EN_GNR;
   wire                         wFM_PVCCFA_EHV_CPU0_R_EN_SPR, wFM_PVCCFA_EHV_CPU1_R_EN_SPR, wFM_PVCCFA_EHV_CPU0_R_EN_GNR, wFM_PVCCFA_EHV_CPU1_R_EN_GNR;
   wire                         wFM_PVNN_MAIN_CPU0_R_EN_SPR, wFM_PVNN_MAIN_CPU1_R_EN_SPR, wFM_PVNN_MAIN_CPU0_R_EN_GNR, wFM_PVNN_MAIN_CPU1_R_EN_GNR;   
   wire                         wCPU0_PWR_FLT_EHV_CPU_SPR, wCPU0_PWR_FLT_PVNN_SPR, wCPU0_PWR_FLT_EHV_CPU_GNR, wCPU0_PWR_FLT_PVNN_GNR;
   wire                         wCPU1_PWR_FLT_EHV_CPU_SPR, wCPU1_PWR_FLT_PVNN_SPR, wCPU1_PWR_FLT_EHV_CPU_GNR, wCPU1_PWR_FLT_PVNN_GNR;
   
   wire                         wFM_P1V1_AUX_EN;
   
   
   wire                         wCPU_MEM_EN;  

   wire                         wFM_PVCCFA_EHV_CPU0_R_EN;
   wire                         wFM_PVCCFA_EHV_FIVRA_CPU0_R_EN;
   wire                         wFM_PVCCINFAON_CPU0_R_EN;
   wire                         wFM_PVNN_MAIN_CPU0_R_EN;
   wire                         wFM_PVCCD_HV_CPU0_R_EN;

   wire                         wFM_PVCCIN_CPU0_R_EN;
   wire                         wCPU0_MEM_PWR_OK;
   wire                         wCPU0_MEM_PWR_FLT;

   wire                         wCPU_PWR_FLT;
   
   wire                         wPWRGD_CPU0_LVC1_R;
   

   wire                         wFM_PVCCFA_EHV_CPU1_R_EN;
   wire                         wFM_PVCCFA_EHV_FIVRA_CPU1_R_EN;
   wire                         wFM_PVCCINFAON_CPU1_R_EN;
   wire                         wFM_PVNN_MAIN_CPU1_R_EN;
   wire                         wFM_PVCCD_HV_CPU1_R_EN;

   wire                         wFM_PVCCIN_CPU1_R_EN;
   wire                         wCPU1_MEM_PWR_OK;
   wire                         wCPU1_MEM_PWR_FLT;
   
   wire                         wFM_PVCC3V3_AUX_CPU1_EN;  
   
   //MEM
   wire                         wCPU0_DIMM_FAULT;
   wire                         wCPU1_DIMM_FAULT;
   wire                         wPWRGD_DRAMPWRGD_CPU0;

   wire                         wMEM0_PWR_FLT;
   
   wire                         wPWRGD_DRAMPWRGD_CPU1;

   wire                         wMEM1_PWR_FLT;
   wire                         wDDR_GLBRST_THERMTRIP_DOWN;
   
   //ADR
   wire                         wADR_EN;
   wire                         wADR_RELEASE;
   
   
   
   //VR BYPASS
   wire                         wFM_P3V3_EN_BP;
   wire                         wFM_PS_EN_R_BP;
   wire                         wFM_AUX_SW_EN_BP;
   wire                         wFM_P5V_EN_BP;
   
   wire                         wFM_P1V0_AUX_EN_BP;
   wire                         wFM_P1V1_AUX_EN_BP;
   
   wire                         wFM_P12V_DIMM_PCIE_SW_CPU0_EN_BP;
   wire                         wFM_P12V_DIMM_PCIE_SW_CPU1_EN_BP; 
   
   wire                         wFM_PVCCFA_EHV_CPU0_R_EN_BP; 
   wire                         wFM_PVNN_MAIN_CPU0_R_EN_BP;    
   wire                         wFM_PVCCD_HV_CPU0_R_EN_BP;    

   wire                         wFM_PVCCFA_EHV_FIVRA_CPU0_R_EN_BP;   
   wire                         wFM_PVCCINFAON_CPU0_R_EN_BP;     
   wire                         wFM_PVCCIN_CPU0_R_EN_BP;    
   
   wire                         wFM_PVCC3V3_AUX_CPU1_EN_BP;    
   
   wire                         wFM_PVCCFA_EHV_CPU1_R_EN_BP;     
   wire                         wFM_PVNN_MAIN_CPU1_R_EN_BP;    
   wire                         wFM_PVCCD_HV_CPU1_R_EN_BP;    

   wire                         wFM_PVCCFA_EHV_FIVRA_CPU1_R_EN_BP;   
   wire                         wFM_PVCCINFAON_CPU1_R_EN_BP;     
   wire                         wFM_PVCCIN_CPU1_R_EN_BP;     

   wire                         wclear_error_state;
   
   /////////////////////////////////////////////////////////////////////////////////
   //////////  FPGA POSTCODES
   /////////////////////////////////////////
   
   wire                         wCPU0_PWR_FLT_EHV_CPU;
   wire                         wCPU0_PWR_FLT_EHV_FIVRA_CPU;
   wire                         wCPU0_PWR_FLT_PVCCINFAON_CPU;
   wire                         wCPU0_PWR_FLT_PVNN;
   wire                         wCPU0_PWR_FLT_PVCCIN;
   wire                         wCPU0_PWR_FLT_PVCCD0_HV;
   wire                         wCPU0_PWR_FLT_PVCCD1_HV;
   
   wire                         wCPU1_PWR_FLT_EHV_CPU;
   wire                         wCPU1_PWR_FLT_EHV_FIVRA_CPU;
   wire                         wCPU1_PWR_FLT_PVCCINFAON_CPU;
   wire                         wCPU1_PWR_FLT_PVNN;
   wire                         wCPU1_PWR_FLT_PVCCIN;
   wire                         wCPU1_PWR_FLT_PVCCD0_HV;
   wire                         wCPU1_PWR_FLT_PVCCD1_HV;
   

   /////////////////////////////////////////////////////////////////////////////////
   //////////  SYNC'ed Signals
   ////////////////////////////////////////////////////////////////////////////////  

   wire                         PWRGD_P3V3_AUX_FF;
   wire                         PWRGD_P1V8_AUX_FF;
   wire                         PWRGD_PS_PWROK_CPU_PLD_R_FF;
   wire                         PWRGD_P3V3_FF;
   wire                         FM_S5_WITH_12V_N_FF;
   wire                         FM_SLPS4_CPU0_CPU_PLD_N_FF;
   wire                         FM_SLPS3_CPU0_CPU_PLD_N_FF;
   wire                         PWRGD_PVCCFA_EHV_CPU0_FF;
   wire                         PWRGD_PVNN_MAIN_CPU0_FF;
   wire                         PWRGD_PVCCD0_HV_CPU0_FF;
   wire                         PWRGD_PVCCD1_HV_CPU0_FF;
   wire                         PWRGD_PVCCFA_EHV_FIVRA_CPU0_FF;
   wire                         PWRGD_PVCCINFAON_CPU0_FF;
   wire                         PWRGD_PVCCIN_CPU0_FF;
   wire                         FM_CPU0_GLB_RST_WARN_PLD_N_FF;
   wire                         FM_SLPS4_CPU1_CPU_PLD_N_FF;
   wire                         FM_SLPS3_CPU1_CPU_PLD_N_FF;
   wire                         PWRGD_PVCCFA_EHV_CPU1_FF;
   wire                         PWRGD_PVNN_MAIN_CPU1_FF;
   wire                         PWRGD_PVCCD0_HV_CPU1_FF;
   wire                         PWRGD_PVCCD1_HV_CPU1_FF;
   wire                         PWRGD_PVCCFA_EHV_FIVRA_CPU1_FF;
   wire                         PWRGD_PVCCINFAON_CPU1_FF;
   wire                         PWRGD_PVCCIN_CPU1_FF;
   wire                         FM_CPU1_GLB_RST_WARN_PLD_N_FF;
   wire                         FP_PWR_BTN_N_FF;
   
   wire                         FM_RST_PERST_BIT0_FF;
   wire                         FM_RST_PERST_BIT1_FF;
   wire                         FM_RST_PERST_BIT3_FF;
   wire                         FM_CPU0_PKGID0_FF;
   wire                         FM_CPU0_PKGID1_FF;
   wire                         FM_CPU0_PKGID2_FF;
   wire                         FM_CPU0_PROC_ID0_FF;
   wire                         FM_CPU0_PROC_ID1_FF;
   wire                         FM_CPU0_SKTOCC_LVT3_PLD_N_FF;
   wire                         FM_CPU1_PKGID0_FF;
   wire                         FM_CPU1_PKGID1_FF;
   wire                         FM_CPU1_PKGID2_FF;
   wire                         FM_CPU1_PROC_ID0_FF;
   wire                         FM_CPU1_PROC_ID1_FF;
   wire                         FM_CPU1_SKTOCC_LVT3_PLD_N_FF;

   wire                         FM_PASSWORD_CLEAR_N_FF;
   wire                         FM_S3M_CPU0_CPLD_CRC_ERROR_FF;
   wire                         FM_S3M_CPU1_CPLD_CRC_ERROR_FF;
   wire                         FM_POSTCODE_PFR_CC_SEL_N_FF;
   wire                         FM_1200VA_OC_FF;
   wire                         IRQ_PMBUS_PLD_ALERT_N_FF;
   wire                         IRQ_CPU0_VRHOT_N_FF;
   wire                         IRQ_CPU1_VRHOT_N_FF;
   wire                         IRQ_CPU0_MEM_VRHOT_N_FF;
   wire                         IRQ_CPU1_MEM_VRHOT_N_FF;
   wire                         FM_ADR_COMPLETE_PLD_FF;
   wire                         FM_ADR_MODE0_FF;
   wire                         FM_ADR_MODE1_FF;
   wire                         FM_CPU0_ADR_TRIGGER_N_FF;
   wire                         FM_CPU0_ADR_EXT_TRIGGER_N_FF;
   wire                         FM_CPU1_ADR_EXT_TRIGGER_N_FF;
   wire                         FM_ADR_COMPLETE_P1_PLD_FF;
   wire                         FM_M2_EDSFF_PRSNT_N_FF;
   wire                         FM_SFFX4_EXPCARD_IO_B_0_FF;
   wire                         PWRGD_OCP0_PWR_FF;
   wire                         FM_OCP0_CARD_PRSNTB_LVC3_N_FF;
   wire                         wFM_HPM_STBY_EN_FF;
   wire                         wFM_HPM_STBY_RST_N_FF;
   wire                         FM_SCM_PRSNT0_LVC3_N_FF;

   wire                         PWRGD_P5V_AUX_FF;
   wire                         FM_CPU0_REFCLK_RDY_PLD_FF;
   wire                         FM_CPU1_REFCLK_RDY_PLD_FF;
   wire                         wFM_PLD_CLKS_DEV_R_EN_psuctrl;
   
   //1.0V Bank signals

   wire                         wH_CPU0_CATERR_LVC1_N;
   wire                         wH_CPU0_RMCA_LVC1_N;
   wire                         wH_CPU1_CATERR_LVC1_N;
   wire                         wH_CPU1_RMCA_LVC1_N;
   
   wire                         H_CPU0_THERMTRIP_LVC1_N_FF;
   wire                         H_CPU1_THERMTRIP_LVC1_N_FF;
   wire                         wH_CPU0_THERMTRIP_LVC1_N;
   wire                         wH_CPU1_THERMTRIP_LVC1_N;
   wire                         wH_CPU_THERMTRIP_LVC1_N;

   wire                         wH_CPU0_MEMTRIP_LVC1_N;
   wire                         wH_CPU1_MEMTRIP_LVC1_N;
   wire                         wH_CPU_MEMTRIP_LVC1_N;
   
   wire                         wH_CPU0_THERMTRIP_LVC1_N_NEGEDGE;
   wire                         wH_CPU1_THERMTRIP_LVC1_N_NEGEDGE;
   reg                          rH_CPU0_THERMTRIP_LVC1_N_LATCHED;
   reg                          rH_CPU1_THERMTRIP_LVC1_N_LATCHED;
   
   	wire                        wH_CPU0_MEMTRIP_LVC1_N_NEGEDGE;
	wire                        wH_CPU1_MEMTRIP_LVC1_N_NEGEDGE;
	reg                         rH_CPU0_MEMTRIP_LVC1_N_LATCHED;
	reg                         rH_CPU1_MEMTRIP_LVC1_N_LATCHED;
   
   //1.1V DDR Signals
   wire                         M_AB_CPU0_RESET_N_FF;   
   wire                         M_CD_CPU0_RESET_N_FF;
   wire                         M_EF_CPU0_RESET_N_FF;
   wire                         M_GH_CPU0_RESET_N_FF;
   
   wire                         M_AB_CPU1_RESET_N_FF;   
   wire                         M_CD_CPU1_RESET_N_FF;
   wire                         M_EF_CPU1_RESET_N_FF;
   wire                         M_GH_CPU1_RESET_N_FF;
   
   wire [(MAIN2MODREGS*8)-1:0]  wSgpioMainModIPData;
   
   wire                         wHeartBeat;
   
   wire                         wStepBPseq;
   
   
   //--------------------------------------------------------------------------------------------------------------------------------
   wire [3:0]                   wUnusedP2;
   wire [6:0]                   wUnusedP1;
   
   //--------------------------------------------------------------------------------------------------------------------------------
   
   wire                         w_1uSCE;
   wire                         w_5uSCE;
   wire                         w_10uSCE;
   wire                         w_50uSCE;
   wire                         w_500uSCE;
   wire                         w_1mSCE;
   wire                         w_20mSCE;
   wire                         w_250mSCE;
   wire                         w_1SCE;
   
   //--------------------------------------------------------------------------------------------------------------------------------
   
   wire                         w_PWRGD_OCP0_PWR_DLY;
   
   //--------------------------------------------------------------------------------------------------------------------------------
   
   wire                         wBPEna, wBPGo, wPvcc3v3AuxCpu1, wP1v0MaxEna,wP1v1MaxEna;
   wire                         wPvccfaEhvCpu0Ena, wPvccfaEhvCpu1Ena, wPvnnAuxCpu0Ena,wPvnnAuxCpu1Ena, wPsuEna,wAuxSwEna;
   wire                         wP12VDimmPcieSwCpu0Ena,wP12VDimmPcieSwCpu1Ena, wPldClksDevEna, wFmP3V3En, wPVccd0HvCpu0Ena,wPVccd1HvCpu0Ena;
   wire                         wPVccd0HvCpu1Ena,wPVccd1HvCpu1Ena, wPvccfaEhvFivraCpu0Ena,wPvccfaEhvFivraCpu1Ena;
   wire                         wPvccInfaOnCpu0Ena,wPvccInfaOnCpu1Ena, wPvccinCpu0Ena,wPvccinCpu1Ena;
   wire                         wFmTs3ds10224EnaOD, wFmTs3ds10224EnbOD, WFmP5VEna;
   
   wire				GLBRST_HOLD_OFF_FF;
   
   wire wDoneTimer_CPU0_PWRGD_1_5ms, wDoneTimer_CPU1_PWRGD_1_5ms;
   localparam T_1_5ms_2M = 12'd3000;
   
   // wires for Blocking Reset
   wire oAsync_GLBRST;
   wire oAsync_WarmR;
   wire oGLBRST_N;
   wire oPLTRST_N;
   wire HCpu0CaterEncode0_sync;
   wire HCpu1CaterEncode0_sync;
   wire HCpu0CaterEncode1_sync;
   wire HCpu1CaterEncode1_sync;
   
   //--------------------------------------------------------------------------------------------------------------------------------

   /////////////////////////////////////////////////////////////////////////////////
   //////////  SYNC'ed Signals, directly to LVDS
   ////////////////////////////////////////////////////////////////////////////////  
   
   //////////////////////////////////////////////////////////////////////////////////
   //CPU0_VNN Rail IO Synchronizer, directly to LVDS link
   
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(7), .RST_VALUE(7'b111_1111)
      )synch_pwrgd_cpu0_lvds        //for 1.0V bank cpu0 signals, directly to LVDS 
       (
        .iClk(iClk_2M),       //input clock
        .iARst_n(iRST_N),       //asynch reset signal active low
        .iEna(1'b1),      //enable signal to capture into the FFs (active high)
        //for N-1, this should not be gating by VNN PWRGD
        .iSRst_n(PWRGD_CPU0_LVC1_R),    //sync rst, when is low, output is reset
        .iSignal({
                  H_CPU0_THERMTRIP_LVC1_N,         //to SCM FPGA thru LVDS   
                  H_CPU0_MEMTRIP_LVC1_N,          //to SCM FPGA thru LVDS
                  H_CPU0_MEMHOT_OUT_LVC1_N,        //to SCM FPGA thru LVDS
                  H_CPU0_ERR0_LVC1_N,            //to SCM FPGA thru LVDS
                  H_CPU0_ERR1_LVC1_N,            //to SCM FPGA thru LVDS
                  H_CPU0_ERR2_LVC1_N,            //to SCM FPGA thru LVDS
                  H_CPU0_MON_FAIL_PLD_LVC1_N      //to SCM FPGA thru LVDS
                  }),
        
        .oFilteredSignals({
                           H_CPU0_THERMTRIP_LVC1_N_FF,  //to SCM FPGA thru LVDS   
                           oH_CPU0_MEMTRIP_LVC1_N,        //to SCM FPGA thru LVDS
                           oH_CPU0_MEMHOT_OUT_LVC1_N,      //to SCM FPGA thru LVDS
                           oH_CPU0_ERR0_LVC1_N,          //to SCM FPGA thru LVDS
                           oH_CPU0_ERR1_LVC1_N,          //to SCM FPGA thru LVDS
                           oH_CPU0_ERR2_LVC1_N,          //to SCM FPGA thru LVDS
                           oH_CPU0_MON_FAIL_PLD_LVC1_N      //to SCM FPGA thru LVDS
                           })       
        );
   
   //////////////////////////////////////////////////////////////////////////////////
         //CPU1_VNN Rail IO Synchronizer, directly to BMC thru LVDS
   
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(7), .RST_VALUE(7'b111_1111)
      )synch_pwrgd_cpu1_lvds        //for 1.0V bank cpu1 signals, directly to LVDS 
       (
        .iClk(iClk_2M),       //input clock
        .iARst_n(iRST_N),       //asynch reset signal active low
        .iEna(1'b1),      //enable signal to capture into the FFs (active high)
        .iSRst_n(PWRGD_CPU1_LVC1_R),
        .iSignal
        ({
          H_CPU1_THERMTRIP_LVC1_N,         //to SCM FPGA thru LVDS   
          H_CPU1_MEMTRIP_LVC1_N,          //to SCM FPGA thru LVDS
          H_CPU1_MEMHOT_OUT_LVC1_N,        //to SCM FPGA thru LVDS
          H_CPU1_ERR0_LVC1_N,            //to SCM FPGA thru LVDS
          H_CPU1_ERR1_LVC1_N,            //to SCM FPGA thru LVDS
          H_CPU1_ERR2_LVC1_N,            //to SCM FPGA thru LVDS
          H_CPU1_MON_FAIL_PLD_LVC1_N      //to SCM FPGA thru LVDS
          }),
        
        .oFilteredSignals
        ({
          H_CPU1_THERMTRIP_LVC1_N_FF,  //to SCM FPGA thru LVDS   
          oH_CPU1_MEMTRIP_LVC1_N,        //to SCM FPGA thru LVDS
          oH_CPU1_MEMHOT_OUT_LVC1_N,      //to SCM FPGA thru LVDS
          oH_CPU1_ERR0_LVC1_N,          //to SCM FPGA thru LVDS
          oH_CPU1_ERR1_LVC1_N,          //to SCM FPGA thru LVDS
          oH_CPU1_ERR2_LVC1_N,          //to SCM FPGA thru LVDS
          oH_CPU1_MON_FAIL_PLD_LVC1_N      //to SCM FPGA thru LVDS
          })       
        );
   
   
   //////////////////////////////////////////////////////////////////////////////////
         //Input signals Synchronizer, directly to BMC thru LVDS
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(18), .RST_VALUE(18'b0_1_1_000_0000_0000_0000)
      )synch_input_lvds   //for all input signals that will directly tunneled to LVDS
       (
        .iClk(iClk_2M),   //input clock
        .iARst_n(iRST_N), //asynch reset signal active low
        .iEna(1'b1),      //enable signal to capture into the FFs (active high)
        .iSRst_n(1'b1),   //sync rst, when is low, output is reset
        .iSignal
        ({
          FM_BMC_SAFS_SEL,

          FP_PWR_BTN_N,

          FM_SMB_BMC_NVME_LVC3_ALERT_N,
          
          FM_BOARD_SKU_ID0,
          FM_BOARD_SKU_ID1,
          FM_BOARD_SKU_ID2,
          
          FM_BOARD_SKU_ID3,
          FM_BOARD_SKU_ID4,
          FM_BOARD_REV_ID0,
          FM_BOARD_REV_ID1,
                  
          FM_BOARD_REV_ID2,
          FM_STANDALONE_MODE_N,
          FM_4S_8S_MODE_N,
          FM_NODE_ID0,
          
          FM_NODE_ID1,
          FM_S3M_CPU0_CPLD_CRC_ERROR,
          FM_S3M_CPU1_CPLD_CRC_ERROR,
          FM_1200VA_OC
          }),
        
        .oFilteredSignals
        ({
          oFM_BMC_SAFS_SEL,
          FP_PWR_BTN_N_FF,
          
          oFM_SMB_BMC_NVME_LVC3_ALERT_N,
          oFM_BOARD_SKU_ID0,
          oFM_BOARD_SKU_ID1,
          oFM_BOARD_SKU_ID2,
          oFM_BOARD_SKU_ID3,
          oFM_BOARD_SKU_ID4,
          oFM_BOARD_REV_ID0,
          oFM_BOARD_REV_ID1,
          oFM_BOARD_REV_ID2,
          oFM_STANDALONE_MODE_N,
          oFM_4S_8S_MODE_N,
          oFM_NODE_ID0,
          oFM_NODE_ID1,
          oFM_S3M_CPU0_CPLD_CRC_ERROR,
          oFM_S3M_CPU1_CPLD_CRC_ERROR,
          oFM_1200VA_OC
          })       
        );  
		
    delay #(.COUNT(T_1_5ms_2M)) 
        Timer1_5ms_CPU0(
            .iClk    ( iClk_2M            ),
            .iRst    ( iRST_N             ),
            .iStart  ( wPWRGD_CPU0_LVC1_R ),   
            .iClrCnt ( 1'b0               ),
            .oDone   ( wDoneTimer_CPU0_PWRGD_1_5ms   )
        );
		
    delay #(.COUNT(T_1_5ms_2M)) 
        Timer1_5ms_CPU1(
            .iClk    ( iClk_2M            ),
            .iRst    ( iRST_N             ),
            .iStart  ( PWRGD_CPU1_LVC1_R ),   
            .iClrCnt ( 1'b0               ),
            .oDone   ( wDoneTimer_CPU1_PWRGD_1_5ms   )
        );
   
   //100M CLK
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(2), .RST_VALUE(2'b11)
      )synch_pwrgd_cpu0_100M        //for 1.0V bank cpu0 signals 
       (
        .iClk(iClk_100M),                           //input clock
        .iARst_n(iRST_N),                           //asynch reset signal active low
        .iEna(1'b1),                                //enable signal to capture into the FFs (active high)
        .iSRst_n(wDoneTimer_CPU0_PWRGD_1_5ms),
        .iSignal
        ({
          H_CPU0_CATERR_LVC1_N,   
          H_CPU0_RMCA_LVC1_N
          }),
        
        .oFilteredSignals
        ({
          wH_CPU0_CATERR_LVC1_N,   
          wH_CPU0_RMCA_LVC1_N
          })       
        );
   
   //------------------------------------------------------------------------------------------------
   //CPU1_VNN Rail IO Synchronizer
   
   //100M CLK
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(2), .RST_VALUE(2'b11)
      )synch_pwrgd_cpu1_100M                         //for 1.0V bank cpu1 signals 
       (
        .iClk(iClk_100M),                           //input clock
        .iARst_n(iRST_N),                           //asynch reset signal active low
        .iEna(1'b1),                                //enable signal to capture into the FFs (active high)
        .iSRst_n(wDoneTimer_CPU1_PWRGD_1_5ms),
        .iSignal
        ({
          H_CPU1_CATERR_LVC1_N,   
          H_CPU1_RMCA_LVC1_N
          }),
        
        .oFilteredSignals
        ({
          wH_CPU1_CATERR_LVC1_N,   
          wH_CPU1_RMCA_LVC1_N
          })       
        );  
   
   
   //------------------------------------------------------------------------------------------------
   //CPU0_VCCD Rail IO Synchronizer
   
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(4), .RST_VALUE(4'b0000)
      )synch_pvccd0_cpu0                   //for 1.1V bank cpu0 signals 
       (
        .iClk(iClk_2M),                    //input clock
        .iARst_n(iRST_N),                  //asynch reset signal active low
        .iEna(1'b1),                       //enable signal to capture into the FFs (active high)
        .iSRst_n(PWRGD_PVCCD0_HV_CPU0),    //sync rst, when is low, output is reset
        .iSignal
        ({
          M_AB_CPU0_RESET_N,   
          M_CD_CPU0_RESET_N,
          M_EF_CPU0_RESET_N,
          M_GH_CPU0_RESET_N

          }),
        
        .oFilteredSignals
        ({
          M_AB_CPU0_RESET_N_FF,   
          M_CD_CPU0_RESET_N_FF,
          M_EF_CPU0_RESET_N_FF,
          M_GH_CPU0_RESET_N_FF

          })       
        );  
   
   //------------------------------------------------------------------------------------------------
   //CPU1_VCCD Rail IO Synchronizer
   
   GlitchFilter # 
     (
      .NUMBER_OF_SIGNALS(4), .RST_VALUE(4'b0000)
      )synch_pvccd0_cpu1                   //for 1.1V bank cpu0 signals 
       (
        .iClk(iClk_2M),                    //input clock
        .iARst_n(iRST_N),                  //asynch reset signal active low
        .iEna(1'b1),                       //enable signal to capture into the FFs (active high)
        .iSRst_n(PWRGD_PVCCD0_HV_CPU1),    //sync rst, when is low, output is reset
        .iSignal
        ({
          M_AB_CPU1_RESET_N,   
          M_CD_CPU1_RESET_N,
          M_EF_CPU1_RESET_N,
          M_GH_CPU1_RESET_N

          }),
        
        .oFilteredSignals
        ({
          M_AB_CPU1_RESET_N_FF,   
          M_CD_CPU1_RESET_N_FF,
          M_EF_CPU1_RESET_N_FF,
          M_GH_CPU1_RESET_N_FF

          })       
        );  
   
   
   //------------------------------------------------------------------------------------------------
   //Inputs Synchronizer
   //------------------------------------------------------------------------------------------------
   GlitchFilter #
     (
      .NUMBER_OF_SIGNALS  (61), .RST_VALUE(61'b1_1_0_0000_10_000_0000_00_000_0010_0__1111_1111_1111_1_1111_1110_0010_1001_001_000)
      ) mGlitchFilter
       (
        .iClk   (iClk_2M),
        .iARst_n(iRST_N),
        .iSRst_n(1'b1),
        .iEna   (1'b1),
        .iSignal
        ({FM_CPU0_ADR_TRIGGER_N,
	
		  FM_RST_PERST_BIT3,
		  
          iGLBRST_HOLD_OFF,
          PWRGD_P3V3_AUX,              
          PWRGD_P1V8_AUX,
          PWRGD_PS_PWROK_CPU_PLD_R,
          PWRGD_P3V3,
          
          FM_S5_WITH_12V_N,
          PWRGD_PVCCFA_EHV_CPU0,
          
          PWRGD_PVNN_MAIN_CPU0,
          PWRGD_PVCCD0_HV_CPU0,
          PWRGD_PVCCD1_HV_CPU0,
          
          PWRGD_PVCCFA_EHV_FIVRA_CPU0,
          PWRGD_PVCCINFAON_CPU0,
          PWRGD_PVCCIN_CPU0,
          FM_CPU0_GLB_RST_WARN_PLD_N,
          
          PWRGD_PVCCFA_EHV_CPU1,
          PWRGD_PVNN_MAIN_CPU1,
          
          PWRGD_PVCCD0_HV_CPU1,
          PWRGD_PVCCD1_HV_CPU1,
          PWRGD_PVCCFA_EHV_FIVRA_CPU1,
          
          PWRGD_PVCCINFAON_CPU1,
          PWRGD_PVCCIN_CPU1,
          FM_CPU1_GLB_RST_WARN_PLD_N,
          FM_RST_PERST_BIT0,
          
          FM_RST_PERST_BIT1,
          
          FM_CPU0_PKGID0,
          FM_CPU0_PKGID1,
          FM_CPU0_PKGID2,
          FM_CPU0_PROC_ID0,
          
          FM_CPU0_PROC_ID1,
          FM_CPU0_SKTOCC_LVT3_PLD_N,
          FM_CPU1_PKGID0,
          FM_CPU1_PKGID1,
          
          FM_CPU1_PKGID2,
          FM_CPU1_PROC_ID0,
          FM_CPU1_PROC_ID1,
          FM_CPU1_SKTOCC_LVT3_PLD_N,
          
          FM_PASSWORD_CLEAR_N,
          
          FM_CPU1_ADR_EXT_TRIGGER_N,
          FM_POSTCODE_PFR_CC_SEL_N,                  
          IRQ_PMBUS_PLD_ALERT_N,
          IRQ_CPU0_VRHOT_N,
          
          IRQ_CPU1_VRHOT_N,
          IRQ_CPU0_MEM_VRHOT_N,                  
          IRQ_CPU1_MEM_VRHOT_N,
          FM_ADR_COMPLETE_PLD,
          
          FM_ADR_MODE0,
          FM_ADR_MODE1,                  
          FM_CPU0_ADR_EXT_TRIGGER_N,
          FM_ADR_COMPLETE_P1_PLD,
          
          FM_M2_EDSFF_PRSNT_N,
          FM_SFFX4_EXPCARD_IO_B_0,                  
          PWRGD_OCP0_PWR,
          FM_OCP0_CARD_PRSNTB_LVC3_N,
          
          FM_HPM_STBY_EN,
          FM_HPM_STBY_RST_N,
          FM_SCM_PRSNT0_LVC3_N, 
          
          PWRGD_P5V_AUX,                  
          FM_CPU0_REFCLK_RDY_PLD,
          FM_CPU1_REFCLK_RDY_PLD
          
          }),
        
        .oFilteredSignals
        ({FM_CPU0_ADR_TRIGGER_N_FF,
		  FM_RST_PERST_BIT3_FF,
	      
		  GLBRST_HOLD_OFF_FF,
          PWRGD_P3V3_AUX_FF,
          PWRGD_P1V8_AUX_FF,
          PWRGD_PS_PWROK_CPU_PLD_R_FF,
          PWRGD_P3V3_FF,
          FM_S5_WITH_12V_N_FF,
          PWRGD_PVCCFA_EHV_CPU0_FF,
          PWRGD_PVNN_MAIN_CPU0_FF,
          PWRGD_PVCCD0_HV_CPU0_FF,
          PWRGD_PVCCD1_HV_CPU0_FF,
          PWRGD_PVCCFA_EHV_FIVRA_CPU0_FF,
          PWRGD_PVCCINFAON_CPU0_FF,
          PWRGD_PVCCIN_CPU0_FF,
          FM_CPU0_GLB_RST_WARN_PLD_N_FF,
          PWRGD_PVCCFA_EHV_CPU1_FF,
          PWRGD_PVNN_MAIN_CPU1_FF,
          PWRGD_PVCCD0_HV_CPU1_FF,
          PWRGD_PVCCD1_HV_CPU1_FF,
          PWRGD_PVCCFA_EHV_FIVRA_CPU1_FF,
          PWRGD_PVCCINFAON_CPU1_FF,
          PWRGD_PVCCIN_CPU1_FF,
          FM_CPU1_GLB_RST_WARN_PLD_N_FF,
          FM_RST_PERST_BIT0_FF,
          FM_RST_PERST_BIT1_FF,
          FM_CPU0_PKGID0_FF,
          FM_CPU0_PKGID1_FF,
          FM_CPU0_PKGID2_FF,
          FM_CPU0_PROC_ID0_FF,
          FM_CPU0_PROC_ID1_FF,
          FM_CPU0_SKTOCC_LVT3_PLD_N_FF,
          FM_CPU1_PKGID0_FF,
          FM_CPU1_PKGID1_FF,
          FM_CPU1_PKGID2_FF,
          FM_CPU1_PROC_ID0_FF,
          FM_CPU1_PROC_ID1_FF,
          FM_CPU1_SKTOCC_LVT3_PLD_N_FF,
          FM_PASSWORD_CLEAR_N_FF,
          FM_CPU1_ADR_EXT_TRIGGER_N_FF,
          FM_POSTCODE_PFR_CC_SEL_N_FF,
          IRQ_PMBUS_PLD_ALERT_N_FF,
          IRQ_CPU0_VRHOT_N_FF,
          IRQ_CPU1_VRHOT_N_FF,
          IRQ_CPU0_MEM_VRHOT_N_FF,
          IRQ_CPU1_MEM_VRHOT_N_FF,
          FM_ADR_COMPLETE_PLD_FF,
          FM_ADR_MODE0_FF,
          FM_ADR_MODE1_FF,
          FM_CPU0_ADR_EXT_TRIGGER_N_FF,
          FM_ADR_COMPLETE_P1_PLD_FF,
          FM_M2_EDSFF_PRSNT_N_FF,
          FM_SFFX4_EXPCARD_IO_B_0_FF,
          PWRGD_OCP0_PWR_FF,
          FM_OCP0_CARD_PRSNTB_LVC3_N_FF,
          wFM_HPM_STBY_EN_FF,
          wFM_HPM_STBY_RST_N_FF,
          FM_SCM_PRSNT0_LVC3_N_FF,
          PWRGD_P5V_AUX_FF,
          FM_CPU0_REFCLK_RDY_PLD_FF,
          FM_CPU1_REFCLK_RDY_PLD_FF
          
          })
        );  

   assign oPWRGD_PVNN_MAIN_CPU0_FF = PWRGD_PVNN_MAIN_CPU0_FF;
   assign oPWRGD_PVNN_MAIN_CPU1_FF = PWRGD_PVNN_MAIN_CPU1_FF;
   

   GlitchFilter2 # (.NUMBER_OF_SIGNALS (2), .RST_VALUE(2'b00))
   Cpu1SlpGlitchFilter
     (
      .iClk(iClk_2M),
      .iARst_n(iRST_N),
      .iSRst_n(PWRGD_AUX_PWRGD_CPU1_PLD),
      .iEna (PWRGD_AUX_PWRGD_CPU1_PLD),
      .iSignal({
                FM_SLPS3_CPU1_CPU_PLD_N,
                FM_SLPS4_CPU1_CPU_PLD_N
                }),
      .oFilteredSignals({
                         FM_SLPS3_CPU1_CPU_PLD_N_FF,
                         FM_SLPS4_CPU1_CPU_PLD_N_FF
                         })
      );


   GlitchFilter2 # (.NUMBER_OF_SIGNALS (2), .RST_VALUE(2'b00))
   Cpu0SlpGlitchFilter
     (
      .iClk(iClk_2M),
      .iARst_n(iRST_N),
      .iSRst_n(PWRGD_AUX_PWRGD_CPU0_PLD),
      .iEna (PWRGD_AUX_PWRGD_CPU0_PLD),
      .iSignal({
                FM_SLPS3_CPU0_CPU_PLD_N,
                FM_SLPS4_CPU0_CPU_PLD_N
                }),
      .oFilteredSignals({
                         FM_SLPS3_CPU0_CPU_PLD_N_FF,
                         FM_SLPS4_CPU0_CPU_PLD_N_FF
                         })
      );
   
   
   //------------------------------------------------------------------------------------------------
   //Instance
   //------------------------------------------------------------------------------------------------
   
   //SYS_CHECK
   sys_check sys_check0
     (
      .iClk(iClk_2M),                                                               //clock for sequential logic 
      .iRst_n(iRST_N),                                                              //reset signal from PLL Lock, resets state machine to initial state
      .ivCPU_SKT_OCC({FM_CPU1_SKTOCC_LVT3_PLD_N_FF, FM_CPU0_SKTOCC_LVT3_PLD_N_FF}), //Socket occupied (input vector for CPU0 and CPU1 SKT_OCC signal)
      .ivPROC_ID_CPU0({FM_CPU0_PROC_ID1_FF, FM_CPU0_PROC_ID0_FF}),                  //CPU0 Processor ID
      .ivPROC_ID_CPU1({FM_CPU1_PROC_ID1_FF, FM_CPU1_PROC_ID0_FF}),                  //CPU1 Processor ID
      .ivPKG_ID_CPU0({FM_CPU0_PKGID2_FF, FM_CPU0_PKGID1_FF, FM_CPU0_PKGID0_FF}),    //CPU0 Package ID
      .ivPKG_ID_CPU1({FM_CPU1_PKGID2_FF, FM_CPU1_PKGID1_FF, FM_CPU1_PKGID0_FF}),    //CPU1 Package ID
      .ivCPU_INTR_CABLE_PRSNT_N({iFM_CPU1_INTR_PRSNT_N, iFM_CPU0_INTR_PRSNT_N}),          //Interposer present, CPU0/1 interposer  // These 2 signals come from debug FPGA via sGPIO
      .oSYS_OK(wSYS_OK),                                                            //System validation Ok, once this module has detected a valid CPU configurqation this signal will be set
      .oCpu0IntrPrsnt_n(wCpu0IntrPrsnt_n),
      .oCpu1IntrPrsnt_n(wCpu1IntrPrsnt_n),
      .oCpu0IntrTypeABn(oCpu0IntrTypeABn),
      .oCpu1IntrTypeABn(oCpu1IntrTypeABn),
      .oCPU_MISMATCH(oCPU_MISMATCH),                                                //CPU Mismatch, if not CPU ID or PKG ID were identified then this signal will remain low, this signal is used in BMC SGPIOs module
      .oHBM(wHBM_EN),                                                               //Output enabler for HBM VR
      .oSOCKET_REMOVED(wSOCKET_REMOVED) ,                                            //Socket Removed
      .rjo_ready  (rjo_ready  ),
      .rjo_ready_sec(rjo_ready_sec)
      
      );
      
      level_sync sync_mcerr0 (.clk(iClk_2M), .signal_in(oH_CPU0_CATERR_LVC1_ENCODE [0] ), .signal_sync(HCpu0CaterEncode0_sync )); 
	  level_sync sync_mcerr1 (.clk(iClk_2M), .signal_in(oH_CPU1_CATERR_LVC1_ENCODE [0] ), .signal_sync(HCpu1CaterEncode0_sync )); 
	  
	  level_sync sync_ierr0 (.clk(iClk_2M), .signal_in(oH_CPU0_CATERR_LVC1_ENCODE [1] ), .signal_sync(HCpu0CaterEncode1_sync )); 
	  level_sync sync_ierr1 (.clk(iClk_2M), .signal_in(oH_CPU1_CATERR_LVC1_ENCODE [1] ), .signal_sync(HCpu1CaterEncode1_sync )); 

   blocking_reset_flow my_blocking_reset_flow
     (
      .iClk          (iClk_2M),                                                                //clock for sequential logic 
      .iRst_n        (iRST_N),                                                                 //reset signal from PLL Lock, resets state machine to initial state
      .iMCERR        (HCpu0CaterEncode0_sync || HCpu1CaterEncode0_sync),       // CATERR_ENCODE [0]
      .iIERR         (HCpu0CaterEncode1_sync || HCpu1CaterEncode1_sync),       // CATERR_ENCODE [1]
      .iPLTRST_N     (iIBL_RDY_N && !wCpu0IntrPrsnt_n ? 1'b0 : iRST_PLTRST_CPU0_PFR_LVC3_N),         
      .iGLBRST_N     (FM_CPU0_GLB_RST_WARN_PLD_N_FF),         
      .iAsync_GLBRST (iFM_GLOBAL_RESET),
      .iAsync_WarmR  (iSURPRISE_RESET),
	  .iPwrBtn_N     (iCPU0_PWRBTN_FPGA_N),
	  .iRstBtn_N     (iCPU0_RSTBTN_FPGA_N),
	  
      .oPLTRST_N     (oPLTRST_N),
      .oGLBRST_N     (oGLBRST_N),
      .oAsync_GLBRST (oAsync_GLBRST),
      .oAsync_WarmR  (oAsync_WarmR)  
      
      );

	  

   assign oCpu0IntrPrsnt_n = wCpu0IntrPrsnt_n;
   assign oCpu1IntrPrsnt_n = wCpu1IntrPrsnt_n;

   wire             wSmbPcieSclSync2M;

   InputsSyncWithDefault # 
     (
      .SIZE       (1 ),
      .DEFAULT_OUT(1'b1  )
      ) InputsSyncWithDefault_2M 
       (
        .i_Clk  ( iClk_2M ),
        .i_Rst_n( iRST_N ), 
        .i_vSync({
                  SMB_PCIE_STBY_LVC3_SCL
                  }),
        .o_vSync({
                  wSmbPcieSclSync2M
                  })
        );
   
   
   
    //Master Seq
    master_fub master_fub_inst
    (
        .iClk(iClk_2M),                                //clock for sequential logic 
        .iRst_n(iRST_N),                               //reset signal from PLL Lock, resets state machine to initial state

        .iLTPI_LINK_ALIGNED(iLTPI_LINK_ALIGNED),       // From IOC module, indicate LTPI link training done, link aligned
        .iSYS_CHECK_OK(wSYS_OK),                       //input System Check is Good. It enables the Master fub execution
        .iINTR_PRSNT_N(wCpu0IntrPrsnt_n),              //Interposer Present, for specifics in the pwer up sequence when there is interposer
        .iBMC_ONCTL_N(iBMC_ONCTL_N),                   //from BMC thru LVDS, FM_BMC_ONCTL_N (active low)
        .iFM_SLP_S3_N(FM_SLPS3_CPU0_CPU_PLD_N_FF),     //Sleep S3 signal
        .iFM_SLP_S4_N(FM_SLPS4_CPU0_CPU_PLD_N_FF),     //Sleep S4 signal
        .iFM_HPM_STBY_EN(wFM_HPM_STBY_EN_FF),          // From DC-SCM, indicate all VRs of DC-SCM modules are on, including DC-SCM card VRs and runBMC VRs
        .iFM_HPM_STBY_RST_N(wFM_HPM_STBY_RST_N_FF),    // From DC-SCM, indicate BMC boot done

        .iCpu0AuxPwrgdPfr(iAUX_PWRGD_CPU0_SCM),        //This comes from PFR and helps indicating special FW update flow (need to be used to go to S5 and toggle S5_PWR_RETAINED and CPU_AUX_PWRGD output)
     
        .iSTBY_PWRGD(PWRGD_P3V3_AUX_FF && PWRGD_P1V8_AUX_FF && PWRGD_P5V_AUX_FF),   // From baseboard stand-by VRs,indicate baseboard stand-by VRs on, including P5V_AUX, P3V3_AUX and P1V8_AUX (on BNC we have these tied to 1 as there is no connection to PLD)
        .iCPU0_AUX_Done(wCPU0_AUX_PWR_OK),             //CPU AUX sequence done      
        .iCPU1_AUX_Done(wCPU1_AUX_PWR_OK),             //CPU AUX sequence done  	  
        .iPSU_Done(wPSU_PWR_OK),                       //PSU_MAIN sequencer done
        .iCPU0_MEM_Done(wCPU0_MEM_PWR_OK),             //CPU0_MEM sequencer done
        .iCPU1_MEM_Done(wCPU1_MEM_PWR_OK),             //indicate all VRs of CPU1 main domain are on
        .iSCM_BMC_FLT(iSCM_BMC_FLT),                   //failure indication from DC-SCM sequencer
        .iCPU_AUX_FLT(oCPU_AUX_PWR_FLT),               //failure indication from CPU AUX sequencer
        .iPSU_FLT(wPSU_PWR_FLT),                       //failure indication from PSU_MAIN sequencer (if PSU or P3V3 fail)
        .iPSU_PWROK_FLT(oPSU_FLT_CODE[0]),             //with this signal we distinguish if the PSU sequencer failure is due to PSU
        .iCPU_PWR_FLT(wCPU_PWR_FLT),                   //failure indication from CPU_MEM sequencer
        .iSOCKET_REMOVED(wSOCKET_REMOVED),             // From sys_check, indicate CPU is removed during runtime

        .iVR_PWROFF_TIMEOUT(wVR_PWROFF_ERR),           // From bnc_cpu_mem_swq, indicate timeout error during certain VR power off
        .iCPU_AUX_VR_PWROFF_ERR(wAUX_VR_PWROFF_ERR),   // From cpu_aux, indicate timeout error during certain VR power off
        .iCPU0_DIMM_FAULT(wCPU0_DIMM_FAULT),           // From ddr5_pwrgd_logic, indicate power failure of CPU0 DIMM
        .iCPU1_DIMM_FAULT(wCPU1_DIMM_FAULT),           // From ddr5_pwrgd_logic, indicate power failure of CPU1 DIMM
        
        .iRST_PLD_PCIE_CPU0_DEV_PERST_R_N(RST_PLD_PCIE_CPU0_DEV_PERST_R_N),    // From perst, indicate CPU0 PCIe devices reset driving by inband reset flows
        .iRST_PLD_PCIE_CPU1_DEV_PERST_R_N(RST_PLD_PCIE_CPU1_DEV_PERST_R_N),    // From perst, indicate CPU1 PCIe devices reset driving by inband reset flows
        .iFM_THERMTRIP_N(wH_CPU_THERMTRIP_LVC1_N && wH_CPU_MEMTRIP_LVC1_N),    // From CPU, indicates processor or memory has reached a temperature beyond which permanent silicon damage may occur
        .iFM_CPU0_REFCLK_RDY(iIBL_RDY_N),                                      // From CPU0, indicate CPU0 reference clock is ready
        .iFM_CPU1_REFCLK_RDY(FM_CPU1_REFCLK_RDY_PLD_FF),                       // From CPU1, indicate CPU1 reference clock is ready
        .iFM_GLBRST_WARN_N(oGLBRST_N),                                          
        .iPLTRST_SYNC_N(oPLTRST_N),                                            
        .iSURPRISE_RESET ( oAsync_WarmR),                                        // From Blocking_reset Flow, From BMC through LVDS and sGPIO, indicate a warm reset triggered by BMC
        .iFM_GLOBAL_RESET( oAsync_GLBRST),                                      // From Blocking_reset Flow, From BMC through LVDS and sGPIO, indicate a global reset triggered by BMC
        .iFM_SERIAL_BOOT(FM_SERIAL_BOOT),                                      // From on-board jumper J8C1, indicate boot mode. HIGH (default) for serial boot and LOW for parallel boot
        .iFM_CPU1_SKTOCC_LVT3_PLD_N(FM_CPU1_SKTOCC_LVT3_PLD_N_FF),             // From CPU1, indicate socket 1 occupation
        .iFM_ADR_MODE0(FM_ADR_MODE0_FF),                                       // From BIOS through vGPIO, indicate ADR mode (Disabled=2'b00, Legacy=2'b01, Emulated DDR5=2'b10,  Emulated Copy to Flash=2'b11)
        .iFM_ADR_MODE1(FM_ADR_MODE1_FF),                                       // From BIOS through vGPIO, indicate ADR mode (BNC only supports Legacy)
        .iADR_ACK_N(1'b0),                                                     // From ADR fub, indicate power down is triggered by ADR flow (used to distinguish when a power down is due to ADR flow
        .iPWR_RESTART(pwr_restart),                                            // From BMC through CSR, force to exit power failure state
        .iFORCE_TO_ENTER_ERR(force_to_enter_err),                              // From BMC through CSR, force to enter power failure state

        .iCpu1IntrClkConfDone(iCpu1IntrClkConfDone || FM_CPU1_SKTOCC_LVT3_PLD_N || wCpu1IntrPrsnt_n),     
        .iMEM_PWR_OK (wPWRGD_DRAMPWRGD_CPU1),	                               
        .iPWRGD_PVNN_MAIN_CPU0(PWRGD_PVNN_MAIN_CPU0_FF),		               
        
        .oCPU0_AUX_EN(wCPU0_AUX_EN),                     //Enable CPU AUX sequencer to start
        .oCPU1_AUX_EN(wCPU1_AUX_EN),                     //Enable CPU AUX sequencer to start 
        .oPSU_EN(wPSU_EN),                               //Enable PSU_MAIN sequencer to start
        .oCPU_MEM_EN(wCPU_MEM_EN),                       //Enable CPU_MEM sequencer to start
        .oADR_EN(wADR_EN),                               //Enable for ADR FSM
        .oADR_RELEASE(wADR_RELEASE),                     //this if for ADR logic to indicate ddr5 logic when to use its own logic or ADR logic to drive PWRGDFAIL & DRAM_RST_N
        //it is asserted when in CPU AUX state and conditions are met to move to PSU state
        //de-asserted when in PSU state and condtions are met to move to CPU_MEM state
        .oAUX_PWRGD_CPU0(wPWRGD_AUX_PWRGD_CPU0),
        .oAUX_PWRGD_CPU1(wPWRGD_AUX_PWRGD_CPU1),  
        .oFM_HPM_STBY_RDY(oFM_HPM_STBY_RDY),             // To DC-SCM, indicate baseboard stand-by VRs on
        .oDDR_GLBRST_THERMTRIP_DOWN(wDDR_GLBRST_THERMTRIP_DOWN),
        .oS0_PWROK_CPU0(PWRGD_S0_PWROK_CPU0_R),          //S0 PWR-OK for CPU0
        .oS0_PWROK_CPU1(PWRGD_S0_PWROK_CPU1_R),          //S0 PWR-OK for CPU1, for partition use only, tie to cpu0 s0_pwrok for no partition mode
        .oPWRGD_CPU0(wPWRGD_CPU0_LVC1_R),                //CPU0 PWRGD
        .oPWRGD_CPU1(PWRGD_CPU1_LVC1_R),                 //CPU1 PWRGD, for partition use only, tie to cpu0 pwrgd for no partition mode
        .oRST_CPU0_RESET_N(RST_CPU0_RESET_R_N),          //CPU0 RESET
        .oRST_CPU1_RESET_N(RST_CPU1_RESET_R_N),          //CPU1 RESET, for partition use only, tie to cpu1 reset for no partition mode
        
        .oS5_PWR_RETAINED(wFM_S5_PWR_RETAINED), //Not used in N-1 interposer
        .oFORCE_TO_ENTER_ERR_CLEAR(force_to_enter_err_clear),  // To global CSR, clear BMC indication
        .oPWR_RESTART_CLEAR(pwr_restart_clear),          // To global CSR, clear BMC indication
        .oCLEAR_ERROR_STATE(wclear_error_state),         // To S0 power domain control module, force to clear power failure status
        
        
        
        .oMASTER_POST_CODE(oMasterCode),                 //to the 7-Seg Displays to know the Master-Seq state
        .pwr_err_source(pwr_err_source),
        
        
        .iCPU0_AUX_PWRGD_POSEDGE          ( PWRGD_AUX_PWRGD_CPU0_PLD_POSEDGE),                              // From PFR filtered, use this rising edge for S5_PWR_RETAINED sample
        .iSMB_PCIE_STBY_LVC3_SCL(wSmbPcieSclSync2M),
        .iLegacyNode (iLegacyNode),
        .iwInModular (iwInModular),
        .iwInRP 		(iwInRP),
        .iGLBRST_HOLD_OFF   (GLBRST_HOLD_OFF_FF),                              // From BMC through CSR, hold off Global Reset flow
        .CurrentTime_Masterfub(CurrentTime_Masterfub),    // To debug FPGA, indicate platform sequence stage
        .rjo_ready (rjo_ready),
        .rjo_ready_sec(rjo_ready_sec),
		
		.oMBVR_ready_sync ( oMBVR_ready_sync ),
        .iMBVR_ready_ack  ( iMBVR_ready_ack  )
		);


//------------------------------------------------------------------------------------------------------------------

   // CPU0_AUX
    cpu_aux cpu0_aux_inst (
        .iClk                   (iClk_2M                     ),
        .iRst_n                 (iRST_N                      ),
        .iFM_INTR_PRSNT_N       (wCpu0IntrPrsnt_n            ),
        .iCPU_AUX_EN            (wCPU0_AUX_EN                ),          // From master_fub, enable legacy CPU AUX power domain
        .iPWRGD_P1V0_AUX        (iPWRGD_P1V0_AUX             ),          // for when using GNR, we need to control VR from here
        .iPWRGD_PVCCFA_EHV_CPU  (PWRGD_PVCCFA_EHV_CPU0_FF    ),          // From CPU0 VCCFA_EHV VR, indicate this VR is fully on
        .iPWRGD_PVNN_MAIN_CPU   (PWRGD_PVNN_MAIN_CPU0_FF     ),          // From CPU0 VNN_MAIN VR, indicate this VR is fully on
        .iclear_error_state     (1'b0                        ),          // BMC cannot force to exit legacy CPU AUX VR failure
        .iPWRGD_P3V3_AUX        (PWRGD_P3V3_AUX_FF           ),          // From baseboard 3V3_AUX VR, indicate this VR is fully on (for T3 timing requirement)
        .iPWRGD_PVNN_MAIN_CPU0  (PWRGD_PVNN_MAIN_CPU0_FF     ),          // From CPU0 VNN_MAIN VR, indicate this VR is fully on (for T4 timing requirement)
		.iIsLegacy              (1'b1                        ),          // This means this is for CPU0 (legacy CPU)
        .oCPU_AUX_PWRGD         (wCPU0_AUX_PWR_OK            ),          // To master_fub, indicate all VRs of CPU0 AUX domain are on
        .oCPU_AUX_PWR_FLT       (wCPU0_AUX_PWR_FLT           ),          // To master_fub, indicate CPU0 AUX VR failure
        .oPWROFF_TIMEOUT_ERR    (wAUX_VR_PWROFF_CPU0_ERR     ),          // To master_fub, indicate timeout error during certain VR power off
        .oCPU_PWR_FLT_EHV       (wCPU0_PWR_FLT_EHV_CPU_GNR   ),          // To debug FPGA through sGPIO, indicate error source is CPU0 VCCFA_EHV VR
        .oCPU_PWR_FLT_PVNN_MAIN (wCPU0_PWR_FLT_PVNN_GNR      ),          // To debug FPGA through sGPIO, indicate error source is CPU0 VNN_MAIN VR
        .oFM_PVCCFA_EHV_CPU_EN  (wFM_PVCCFA_EHV_CPU0_R_EN_GNR),          // To CPU0 VCCFA_EHV VR, enable this VR
        .oFM_P1V0_AUX_EN        (wFM_P1V0_AUX_CPU0_EN_GNR    ),          // for when using GNR, we need to control VR from here
        .oFM_PVNN_MAIN_CPU_EN   (wFM_PVNN_MAIN_CPU0_R_EN_GNR ),           // To CPU0 VNN_MAIN VR, enable this VR
		.iPWRGD_P1V2_MAX10_AUX_PLD_R_LVC3(PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3)
    );

// CPU1_AUX
    cpu_aux cpu1_aux_inst (
        .iClk                   (iClk_2M                     ),
        .iRst_n                 (iRST_N                      ),
        .iFM_INTR_PRSNT_N       (wCpu1IntrPrsnt_n            ),
        .iCPU_AUX_EN            (!FM_CPU1_SKTOCC_LVT3_PLD_N_FF && wCPU1_AUX_EN ),  // From master_fub, enable non-legacy CPU AUX power domain
        .iPWRGD_P1V0_AUX        (iPWRGD_P1V0_AUX             ),          // for when using GNR, we need to control VR from here
        .iPWRGD_PVCCFA_EHV_CPU  (PWRGD_PVCCFA_EHV_CPU1_FF    ),          // From CPU1 VCCFA_EHV VR, indicate this VR is fully on
        .iPWRGD_PVNN_MAIN_CPU   (PWRGD_PVNN_MAIN_CPU1_FF     ),          // From CPU1 VNN_MAIN VR, indicate this VR is fully on
        .iclear_error_state     (wclear_error_state          ),          // From master_fub, indicate BMC force to exit error state
        .iPWRGD_P3V3_AUX        (1'b1                        ),          // Non-legacy CPU AUX powe domain doesn't need to care T3 timing requirement
        .iPWRGD_PVNN_MAIN_CPU0  (PWRGD_PVNN_MAIN_CPU1_FF     ),          // Non-legacy CPU AUX powe domain doesn't need to care T4 timing requirement
		  .iIsLegacy              (1'b0                        ),          // This means this is for CPU1 (Non-legacy CPU)
        .oCPU_AUX_PWRGD         (wCPU1_AUX_PWR_OK            ),          // To master_fub, indicate all VRs of CPU1 AUX domain are on
        .oCPU_AUX_PWR_FLT       (wCPU1_AUX_PWR_FLT           ),          // To master_fub, indicate CPU1 AUX VR failure
        .oPWROFF_TIMEOUT_ERR    (wAUX_VR_PWROFF_CPU1_ERR     ),          // To master_fub, indicate timeout error during certain VR power off
        .oCPU_PWR_FLT_EHV       (wCPU1_PWR_FLT_EHV_CPU_GNR   ),          // To debug FPGA through sGPIO, indicate error source is CPU1 VCCFA_EHV VR
        .oCPU_PWR_FLT_PVNN_MAIN (wCPU1_PWR_FLT_PVNN_GNR      ),          // To debug FPGA through sGPIO, indicate error source is CPU1 VNN_MAIN VR
        .oFM_PVCCFA_EHV_CPU_EN  (wFM_PVCCFA_EHV_CPU1_R_EN_GNR),          // To CPU1 VCCFA_EHV VR, enable this VR
        .oFM_P1V0_AUX_EN        (wFM_P1V0_AUX_CPU1_EN_GNR    ),          // for when using GNR, we need to control VR from here
        .oFM_PVNN_MAIN_CPU_EN   (wFM_PVNN_MAIN_CPU1_R_EN_GNR ),           // To CPU1 VNN_MAIN VR, enable this VR
		.iPWRGD_P1V2_MAX10_AUX_PLD_R_LVC3(PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3)
    );


   assign PWRGD_AUX_PWRGD_CPU0_PLD = wCPU0_AUX_EN ? wPWRGD_AUX_PWRGD_CPU0 : LOW;    // To CPU0, indicate CPU0 VCCFA_EHV and VNN power rails are fully on and CPU0 IFWI SPI flash verified, can start to boot S3M
   assign PWRGD_AUX_PWRGD_CPU1_PLD = wCPU1_AUX_EN ? wPWRGD_AUX_PWRGD_CPU1 : LOW;    // To CPU1, indicate CPU1 VCCFA_EHV and VNN power rails are fully on and CPU1 IFWI SPI flash verified, can start to boot S3M (Reserve for partition usage)
   assign FM_S5_PWR_RETAINED_CPU0_PLD  = rAUX_PWRGD_CPU0_SCM_NEGEDEG_LATCHED ? LOW : wFM_S5_PWR_RETAINED;

   assign oCPU1_AUX_PWR_OK         = wCPU1_AUX_PWR_OK;                 // To SCM FPGA through LTPI
   assign oCPU_AUX_PWR_FLT         = wCPU0_AUX_PWR_FLT || wCPU1_AUX_PWR_FLT;    // To debug FPGA through sGPIO and to DC-SCM thru LVDS

   assign oCPU0_AUX_PWR_OK         = wCPU0_AUX_PWR_OK;
//------------------------------------------------------------------------------------------------------------------
   
   //PSU ON CONTROL
   psu_ctrl psu_ctrl_inst
     (
      .iClk(iClk_2M),                                   //clock for sequential logic 
      .iRst_n(iRST_N),                                  //reset signal from PLL Lock, resets state machine to initial state  
      .iPsu_enable(wPSU_EN),                            //comming from master seq, triggerred by BMC_ONCTL_N
      .iFM_S5_WITH_12V_N(FM_S5_WITH_12V_N_FF),          //Active low, indicate that 12V main power should be open even in S5 state
      .iPWRGD_PS_PWROK(PWRGD_PS_PWROK_CPU_PLD_R_FF),    //Signal generated by the PSU, indicates when 12V Main is stablished
      .iPWRGD_P3V3(PWRGD_P3V3_FF),                      //Power good coming from 3.3V voltage regulator (powered by 12V main)
      .iClear_error_state(wclear_error_state),          //From master_fub, indicate BMC force to exit error state
      
      .oFM_PS_EN(wFM_PS_EN_R),                          //Enables PSU
      .oFM_P5V_SW_EN(wFM_P5V_EN),                       //Enable P5V Main power switch
      .oFM_P3V3_EN(wFM_P3V3_EN),                        //Enable P3V3 Main VR
      .oFM_AUX_SW_EN(wFM_AUX_SW_EN),                    //Enable P12V_AUX Switch
      .oFM_P12V_DIMM_PCIE_SW_CPU0_EN(wFM_P12V_DIMM_PCIE_SW_CPU0_EN),      //Enable P12V MIAN power for CPU0 Memory and PCIe devices
      .oFM_P12V_DIMM_PCIE_SW_CPU1_EN(wFM_P12V_DIMM_PCIE_SW_CPU1_EN),      //Enable P12V MIAN power for CPU1 Memory and PCIe devices
      .oFM_PLD_CLKS_DEV_EN(oFM_PLD_CLKS_DEV_R_EN),                        //output reg to enable 100MHz external generator from CK440
      
      .oPSU_FAULT(oPSU_FAULT),
      .oP3V3_FAULT(oP3V3_FAULT),
      
      .oDone(wPSU_PWR_OK),                               //Indicates if the function is done
      .oFault(wPSU_PWR_FLT),                             //Failure output reg, to indicate to master sequencer that something failed on this block
      .oFaultCode(oPSU_FLT_CODE),                         //This output reg indicates to Master which is the code of the failure
      .rjo_ready(rjo_ready),
      .rjo_ready_sec(rjo_ready_sec)
      
      );  

    ADR_fub ADR_fub_inst(
        .iClk                       (iClk_2M), 
        .iRst_n                     (iRST_N), 
        .rstatus                    (oMasterCode),
        .FM_ADR_MODE0               (FM_ADR_MODE0_FF),	
        .iFM_ADR_COMPLETE_PLD       (FM_ADR_COMPLETE_PLD_FF ), 
        .iFM_CPU0_ADR_EXT_TRIGGER_N (FM_CPU0_ADR_EXT_TRIGGER_N_FF && FM_CPU0_ADR_TRIGGER_N_FF),
        .iFM_GLOBAL_RESET           (FM_CPU0_GLB_RST_WARN_PLD_N_FF), 
		.iPS_EN                     (wFM_PS_EN_R),
        .iPWRGD_PS_PWROK            (PWRGD_PS_PWROK_CPU_PLD_R_FF),
        .oFM_CPU0_ADR_TRIGGER_N     (oFM_CPU0_ADR_TRIGGER_N),
        .ADRcounter1                (ADRcounter1),
        .ADRcounter2                (ADRcounter2)
    );
    
   //CPU_MEM_SEQ CPU0
   bnc_cpu_mem_seq bnc_cpu0_mem_seq_inst(
                                              .iClk(iClk_2M),                                               //clock for sequential logic 
                                              .iRst_n(iRST_N),                                              //reset signal from PLL Lock, resets state machine to initial state
                                              
                                              .iCPU_PWR_EN(wCPU_MEM_EN),                                    //Cpu power sequence enable
                                              .iENABLE_TIME_OUT(LOW),                                       //Enable the Timeout                                         
                                              .iFM_INTR_PRSNT_N(wCpu0IntrPrsnt_n),                          //Detect Interposer
                                              .iFM_CPU_SKTOCC_N(FM_CPU0_SKTOCC_LVT3_PLD_N),                 //Socket occupy
                                              .iINTR_ID(),                                                  //Detect Interposer ID (0 = INTRA or 1 = INTRB), signal from sGPIO
                                              .iPWRGD_PVCCFA_EHV_CPU(PWRGD_PVCCFA_EHV_CPU0_FF),             //CPU VR PWRGD PVCCFA_EHV //used here only when interposer is present
                                              .iPWRGD_PVCCFA_EHV_FIVRA_CPU(PWRGD_PVCCFA_EHV_FIVRA_CPU0_FF), //CPU VR PWRGD PVCCFA_EHV_FIVRA
                                              .iPWRGD_PVCCINFAON_CPU(PWRGD_PVCCINFAON_CPU0_FF),             //CPU VR PWRGD PVCCINFAON
                                              .iPWRGD_PVNN_MAIN_CPU(PWRGD_PVNN_MAIN_CPU0_FF),               //CPU VR PWRGD PVNN //used here only when interposer is present
                                              .iPWRGD_PVCCD0_HV_CPU(PWRGD_PVCCD0_HV_CPU0_FF),               //CPU VR MEMORY PWRGD PVCCD0_HV
                                              .iPWRGD_PVCCD1_HV_CPU(PWRGD_PVCCD1_HV_CPU0_FF),               //CPU VR MEMORY PWRGD PVCCD1_HV
                                              .iPWRGD_PVCCIN_CPU(PWRGD_PVCCIN_CPU0_FF),                     //CPU VR PVCCIN
                                              .iclear_error_state(wclear_error_state),                      //from master_fub, indicate BMC force to exit error state
                                              //MEMORY DDR5 Inputs/Outputs     //---------------------------------------------------------------
                                              .oMEM_PWR_FLT(wMEM0_PWR_FLT),                                 //Fault Memory VR
                                              .oMEM_PWR_OK(wPWRGD_DRAMPWRGD_CPU0),                          //PWRGD of MEMORY

                                              //------------------------------------------------------------------------------------------------
                                              
                                              .oFM_PVCCFA_EHV_CPU_EN(wFM_PVCCFA_EHV_CPU0_R_EN_SPR),        //CPU VR EN PVCCFA_EHV //used here only when interposer is present
                                              .oFM_PVCCFA_EHV_FIVRA_CPU_EN(wFM_PVCCFA_EHV_FIVRA_CPU0_R_EN), //CPU VR EN PVCCFA_EHV_FIVRA
                                              .oFM_PVCCINFAON_CPU_EN(wFM_PVCCINFAON_CPU0_R_EN),             //CPU VR EN PVCCINFAON
                                              .oFM_PVNN_MAIN_CPU_EN(wFM_PVNN_MAIN_CPU0_R_EN_SPR),          //CPU VR EN PVNN //used here only when interposer is present
                                              .oFM_PVCCD_HV_CPU_EN(wFM_PVCCD_HV_CPU0_R_EN),                 //CPU VR EN MEMORY PVCCD0_HV

                                              .oFM_PVCCIN_CPU_EN(wFM_PVCCIN_CPU0_R_EN),                     //CPU VR EN PVCCIN

                                              .oVR_PWROFF_TIMEOUT_ERR(wVR_PWROFF_CPU0_ERR),                 // To master_fub, indicate timeout error during certain VR power off
                                              .oFM_PVCC3V3_AUX_CPU_EN(),                                    // CPU0 doesn't need this, this rail of legacy CPU is controlled by board
                                              
                                              .oCPU_PWR_OK(wCPU0_MEM_PWR_OK),                               //PWRGD of all CPU VR's   
                                              .oCPU_PWR_FLT(wCPU0_MEM_PWR_FLT),                             //Fault CPU VR's
                                              
                                              .oCPU_PWR_FLT_EHV_CPU(wCPU0_PWR_FLT_EHV_CPU_SPR),            //Fault  PVCCFA_EHV //used here only when interposer is present
                                              .oCPU_PWR_FLT_EHV_FIVRA_CPU(wCPU0_PWR_FLT_EHV_FIVRA_CPU),     //Fault  PVCCFA_EHV_FIVRA
                                              .oCPU_PWR_FLT_PVCCINFAON_CPU(wCPU0_PWR_FLT_PVCCINFAON_CPU),   //Fault  PVCCINFAON
                                              .oCPU_PWR_FLT_PVNN(wCPU0_PWR_FLT_PVNN_SPR),                  //Fault  PVNN //used here only when interposer is present
                                              .oCPU_PWR_FLT_PVCCIN(wCPU0_PWR_FLT_PVCCIN),                   //Fault  PVCCIN
                                              .oCPU_PWR_FLT_PVCCD0_HV(wCPU0_PWR_FLT_PVCCD0_HV),             //Fault  PVCCD0_HV
                                              .oCPU_PWR_FLT_PVCCD1_HV(wCPU0_PWR_FLT_PVCCD1_HV),             //Fault  PVCCD1_HV

                                              .iPWRGD_P1V0_AUX(iPWRGD_P1V0_AUX),                            //used here only when interposer is present
                                              .iPWRGD_P1V1_AUX(iPWRGD_P1V1_AUX),
                                              .oFM_P1V0_AUX_EN(wFM_P1V0_AUX_CPU0_EN_SPR),                  //used here only when interposer is present
                                              .oFM_P1V1_AUX_EN(wFM_P1V1_AUX_CPU0_EN)
                                              
   
                                              
                                              ); 
   
   //CPU_MEM_SEQ CPU1
   bnc_cpu_mem_seq bnc_cpu1_mem_seq_inst(
                                              
                                              .iClk(iClk_2M),                                               //clock for sequential logic 
                                              .iRst_n(iRST_N),                                              //reset signal from PLL Lock, resets state machine to initial state
                                              
                                              .iCPU_PWR_EN(wCPU_MEM_EN),                                    //Cpu power sequence enable
                                              .iENABLE_TIME_OUT(LOW),                                       //Enable the Timeout
                                              .iFM_INTR_PRSNT_N(wCpu1IntrPrsnt_n),                          //Detect Interposer
                                              .iFM_CPU_SKTOCC_N(FM_CPU1_SKTOCC_LVT3_PLD_N),                 //Socket occupy
                                              .iINTR_ID(),                                                  //Detect Interposer ID (0 = INTRA or 1 = INTRB), signal from sGPIO
                                              .iPWRGD_PVCCFA_EHV_CPU(PWRGD_PVCCFA_EHV_CPU1_FF),             //CPU VR PWRGD PVCCFA_EHV //used here only when interposer is present
                                              .iPWRGD_PVCCFA_EHV_FIVRA_CPU(PWRGD_PVCCFA_EHV_FIVRA_CPU1_FF), //CPU VR PWRGD PVCCFA_EHV_FIVRA
                                              .iPWRGD_PVCCINFAON_CPU(PWRGD_PVCCINFAON_CPU1_FF),             //CPU VR PWRGD PVCCINFAON
                                              .iPWRGD_PVNN_MAIN_CPU(PWRGD_PVNN_MAIN_CPU1_FF),               //CPU VR PWRGD PVNN //used here only when interposer is present
                                              .iPWRGD_PVCCD0_HV_CPU(PWRGD_PVCCD0_HV_CPU1_FF),               //CPU VR MEMORY PWRGD PVCCD0_HV
                                              .iPWRGD_PVCCD1_HV_CPU(PWRGD_PVCCD1_HV_CPU1_FF),               //CPU VR MEMORY PWRGD PVCCD1_HV
                                              .iPWRGD_PVCCIN_CPU(PWRGD_PVCCIN_CPU1_FF),                     //CPU VR PVCCIN
                                              
                                              //MEMORY DDR5 Inputs/Outputs     //---------------------------------------------------------------
                                              .oMEM_PWR_FLT(wMEM1_PWR_FLT),                                 //Fault Memory VR
                                              .oMEM_PWR_OK(wPWRGD_DRAMPWRGD_CPU1),                          //PWRGD of MEMORY

                                              //------------------------------------------------------------------------------------------------
                                              
                                              .oFM_PVCCFA_EHV_CPU_EN(wFM_PVCCFA_EHV_CPU1_R_EN_SPR),        //CPU VR EN PVCCFA_EHV //used here only when interposer is present
                                              .oFM_PVCCFA_EHV_FIVRA_CPU_EN(wFM_PVCCFA_EHV_FIVRA_CPU1_R_EN), //CPU VR EN PVCCFA_EHV_FIVRA
                                              .oFM_PVCCINFAON_CPU_EN(wFM_PVCCINFAON_CPU1_R_EN),             //CPU VR EN PVCCINFAON
                                              .oFM_PVNN_MAIN_CPU_EN(wFM_PVNN_MAIN_CPU1_R_EN_SPR),          //CPU VR EN PVNN //used here only when interposer is present
                                              .oFM_PVCCD_HV_CPU_EN(wFM_PVCCD_HV_CPU1_R_EN),                 //CPU VR EN MEMORY PVCCD0_HV

                                              .oFM_PVCCIN_CPU_EN(wFM_PVCCIN_CPU1_R_EN),                     //CPU VR EN PVCCIN

                                              .oVR_PWROFF_TIMEOUT_ERR(wVR_PWROFF_CPU1_ERR),                 // To master_fub, indicate timeout error during certain VR power off
                                              .oFM_PVCC3V3_AUX_CPU_EN(wFM_PVCC3V3_AUX_CPU1_EN),             //Only valid for CPU1, always on for INTR, enable at S0 for GNR
                                              
                                              .oCPU_PWR_OK(wCPU1_MEM_PWR_OK),                               //PWRGD of all CPU VR's   
                                              .oCPU_PWR_FLT(wCPU1_MEM_PWR_FLT),                             //Fault CPU VR's
                                              
                                              .oCPU_PWR_FLT_EHV_CPU(wCPU1_PWR_FLT_EHV_CPU_SPR),                 //Fault  PVCCFA_EHV
                                              .oCPU_PWR_FLT_EHV_FIVRA_CPU(wCPU1_PWR_FLT_EHV_FIVRA_CPU),     //Fault  PVCCFA_EHV_FIVRA
                                              .oCPU_PWR_FLT_PVCCINFAON_CPU(wCPU1_PWR_FLT_PVCCINFAON_CPU),   //Fault  PVCCINFAON
                                              .oCPU_PWR_FLT_PVNN(wCPU1_PWR_FLT_PVNN_SPR),                       //Fault  PVNN
                                              .oCPU_PWR_FLT_PVCCIN(wCPU1_PWR_FLT_PVCCIN),                   //Fault  PVCCIN
                                              .oCPU_PWR_FLT_PVCCD0_HV(wCPU1_PWR_FLT_PVCCD0_HV),             //Fault  PVCCD0_HV
                                              .oCPU_PWR_FLT_PVCCD1_HV(wCPU1_PWR_FLT_PVCCD1_HV),             //Fault  PVCCD1_HV

                                              .iPWRGD_P1V0_AUX(iPWRGD_P1V0_AUX),                            //used here only when interposer is present
                                              .iPWRGD_P1V1_AUX(iPWRGD_P1V1_AUX),
                                              .oFM_P1V0_AUX_EN(wFM_P1V0_AUX_CPU1_EN_SPR),
                                              .oFM_P1V1_AUX_EN(wFM_P1V1_AUX_CPU1_EN)
                                                                                            
                                              );
   
   //in order to support both sequences, we are combining here the signals from the two different sequencers, which should only
   //enable its respective signal depending on interposer present signal
   assign wFM_P1V0_AUX_EN = wFM_P1V0_AUX_CPU0_EN_SPR || wFM_P1V0_AUX_CPU1_EN_SPR || wFM_P1V0_AUX_CPU0_EN_GNR || wFM_P1V0_AUX_CPU1_EN_GNR;
   assign wFM_P1V1_AUX_EN = wFM_P1V1_AUX_CPU0_EN || wFM_P1V1_AUX_CPU1_EN;

   assign wFM_PVCCFA_EHV_CPU0_R_EN = wFM_PVCCFA_EHV_CPU0_R_EN_SPR  || wFM_PVCCFA_EHV_CPU0_R_EN_GNR;
   assign wFM_PVCCFA_EHV_CPU1_R_EN = wFM_PVCCFA_EHV_CPU1_R_EN_SPR  || wFM_PVCCFA_EHV_CPU1_R_EN_GNR;
   assign wFM_PVNN_MAIN_CPU0_R_EN  = wFM_PVNN_MAIN_CPU0_R_EN_SPR || wFM_PVNN_MAIN_CPU0_R_EN_GNR;
   assign wFM_PVNN_MAIN_CPU1_R_EN  = wFM_PVNN_MAIN_CPU1_R_EN_SPR || wFM_PVNN_MAIN_CPU1_R_EN_GNR;

   assign wCPU0_PWR_FLT_EHV_CPU    = wCPU0_PWR_FLT_EHV_CPU_SPR || wCPU0_PWR_FLT_EHV_CPU_GNR;
   assign wCPU1_PWR_FLT_EHV_CPU    = wCPU1_PWR_FLT_EHV_CPU_SPR || wCPU1_PWR_FLT_EHV_CPU_GNR;
   assign wCPU0_PWR_FLT_PVNN       = wCPU0_PWR_FLT_PVNN_SPR    || wCPU0_PWR_FLT_PVNN_GNR;
   assign wCPU1_PWR_FLT_PVNN       = wCPU1_PWR_FLT_PVNN_SPR    || wCPU1_PWR_FLT_PVNN_GNR;
   
   //DDR5 PWRGD LOGic for CPU0
   ddr5_pwrgd_logic_modular 
     #(
       .MC_SIZE(4)
       ) ddr5_pwrgd_logic_modular_cpu0
       (
        .iClk(iClk_2M),                                //clock for sequential logic 
        .iRst_n(iRST_N),                               //reset signal from PLL Lock, resets state machine to initial state
        
        .iFM_SLPS4_N(FM_SLPS4_CPU0_CPU_PLD_N_FF),      //SLP_S4 indication
        .iPWRGD_PS_PWROK(PWRGD_PS_PWROK_CPU_PLD_R_FF), //PSU PWRGD
        
        .iDDRIO_PWRGD(wPWRGD_DRAMPWRGD_CPU0),          //DRAMPWRGD for valid DIMM FAIL detection
        .iMC_RST_N
        ({
          M_AB_CPU0_RESET_N_FF,
          M_CD_CPU0_RESET_N_FF,
          M_EF_CPU0_RESET_N_FF,
          M_GH_CPU0_RESET_N_FF

          }),                                         //Reset from memory controller
        .iDDR_GLBRST_THERMTRIP_DOWN(wDDR_GLBRST_THERMTRIP_DOWN || !PWRGD_PVCCD0_HV_CPU0_FF),
        .ioPWRGD_FAIL_CH_DIMM_CPU
        ({
          PWRGD_FAIL_CPU0_AB_PLD,
          PWRGD_FAIL_CPU0_CD_PLD,
          PWRGD_FAIL_CPU0_EF_PLD,
          PWRGD_FAIL_CPU0_GH_PLD

          }),                                         //PWRGD_FAIL bidirectional signal
        
        .oDIMM_MEM_FLT(oCPU0_DIMM_FLT_CODE),          //MEM Fault
        .oPWRGD_DRAMPWRGD_OK
        ({
          PWRGD_DRAMPWRGD_CPU0_AB_R_LVC1,
          PWRGD_DRAMPWRGD_CPU0_CD_R_LVC1,
          PWRGD_DRAMPWRGD_CPU0_EF_R_LVC1,
          PWRGD_DRAMPWRGD_CPU0_GH_R_LVC1

          }),                                         //DRAM PWR OK
        .oFPGA_DIMM_RST_N
        ({
          M_AB_CPU0_FPGA_RESET_R_N,
          M_CD_CPU0_FPGA_RESET_R_N,
          M_EF_CPU0_FPGA_RESET_R_N,
          M_GH_CPU0_FPGA_RESET_R_N

          })                                          //Reset to DIMMs
        );
   
   //DDR5 PWRGD LOGic for CPU1
   ddr5_pwrgd_logic_modular 
     #(
       .MC_SIZE(4)
       ) ddr5_pwrgd_logic_modular_cpu1
       (
        .iClk(iClk_2M),                                 //clock for sequential logic 
        .iRst_n(iRST_N),                                //reset signal from PLL Lock, resets state machine to initial state
        
        .iFM_SLPS4_N(FM_SLPS4_CPU0_CPU_PLD_N_FF),       //In partition mode, this should be FM_SLPS4_CPU1_CPU_PLD_N_FF
        .iPWRGD_PS_PWROK(PWRGD_PS_PWROK_CPU_PLD_R_FF),  //PSU PWRGD
        
        .iDDRIO_PWRGD(wPWRGD_DRAMPWRGD_CPU1),           //DRAMPWRGD for valid DIMM FAIL detection
        .iMC_RST_N
        ({
          M_AB_CPU1_RESET_N_FF,
          M_CD_CPU1_RESET_N_FF,
          M_EF_CPU1_RESET_N_FF,
          M_GH_CPU1_RESET_N_FF

          }),                                           //Reset from memory controller
        .iDDR_GLBRST_THERMTRIP_DOWN(wDDR_GLBRST_THERMTRIP_DOWN  || !PWRGD_PVCCD1_HV_CPU0_FF),
        .ioPWRGD_FAIL_CH_DIMM_CPU
        ({
          PWRGD_FAIL_CPU1_AB_PLD,
          PWRGD_FAIL_CPU1_CD_PLD,
          PWRGD_FAIL_CPU1_EF_PLD,
          PWRGD_FAIL_CPU1_GH_PLD
 
          }),                                           //PWRGD_FAIL bidirectional signal
        
        .oDIMM_MEM_FLT(oCPU1_DIMM_FLT_CODE),            //MEM Fault
        .oPWRGD_DRAMPWRGD_OK
        ({
          PWRGD_DRAMPWRGD_CPU1_AB_R_LVC1,
          PWRGD_DRAMPWRGD_CPU1_CD_R_LVC1,
          PWRGD_DRAMPWRGD_CPU1_EF_R_LVC1,
          PWRGD_DRAMPWRGD_CPU1_GH_R_LVC1

          }),                                           //DRAM PWR OK
        .oFPGA_DIMM_RST_N
        ({
          M_AB_CPU1_FPGA_RESET_R_N,
          M_CD_CPU1_FPGA_RESET_R_N,
          M_EF_CPU1_FPGA_RESET_R_N,
          M_GH_CPU1_FPGA_RESET_R_N

          })                                           //Reset to DIMMs
        );     


   //----------------------------------------------------------------------------------------

   // CPU0 PERST
    perst perst_cpu0_inst (
        .iClk                            ( iClk_2M                         ),
        .iRst_n                          ( iRST_N                          ),

        .iPWRGD_CPU                      ( wPWRGD_CPU0_LVC1_R              ),       // From master_fub, indicate CPU0 power good
        .iPLTRST_N                       ( iRST_PLTRST_CPU0_PFR_LVC3_N     ),       // From CPU after PFR filtering, indicate to the platform to reset platform functions
        .iFM_RST_PERST_BIT               ( FM_RST_PERST_BIT0_FF            ),       // From on-board jumper J8A8, choose PERST follow which signal
        .FM_PERST_TIMING_SEL             ( FM_PERST_TIMING_SEL             ),       // From on-board jumper J8A9, choose delay timing parameter
		.iRST_CPU_RESET_R_N              ( RST_CPU0_RESET_R_N              ),
        .oRST_PLD_PCIE_CPU_DEV_PERST_R_N ( RST_PLD_PCIE_CPU0_DEV_PERST_R_N )        // To PCIe divices, trigger to reset PCIe devices
    );

// CPU1 PERST
    perst perst_cpu1_inst (
        .iClk                            ( iClk_2M                         ),
        .iRst_n                          ( iRST_N                          ),

        .iPWRGD_CPU                      ( PWRGD_CPU1_LVC1_R               ),       // From master_fub, indicate CPU1 power good
        .iPLTRST_N                       ( iRST_PLTRST_CPU0_PFR_LVC3_N     ),       // From CPU after PFR filtering, indicate to the platform to reset platform functions
        .iFM_RST_PERST_BIT               ( FM_RST_PERST_BIT1_FF            ),       // From on-board jumper J8B8, choose PERST follow which signal
        .FM_PERST_TIMING_SEL             ( FM_PERST_TIMING_SEL             ),       // From on-board jumper J8A9, choose delay timing parameter
		.iRST_CPU_RESET_R_N              ( RST_CPU1_RESET_R_N              ),
        .oRST_PLD_PCIE_CPU_DEV_PERST_R_N ( RST_PLD_PCIE_CPU1_DEV_PERST_R_N )        // To PCIe divices, trigger to reset PCIe devices
    );
   
   // X16 PERST
   	assign RST_PLD_PCIE_CPU0_x16_PERST = RST_PLD_PCIE_CPU0_DEV_PERST_R_N;

// DCSCM PERST
    perst perst_DCSCM_inst (
        .iClk                            ( iClk_2M                         ),
        .iRst_n                          ( iRST_N                          ),

        .iPWRGD_CPU                      ( wPWRGD_CPU0_LVC1_R               ),       // From master_fub, indicate CPU0 power good
        .iPLTRST_N                       ( iRST_PLTRST_CPU0_PFR_LVC3_N     ),       // From CPU after PFR filtering, indicate to the platform to reset platform functions
        .iFM_RST_PERST_BIT               ( FM_RST_PERST_BIT3_FF            ),       // choose PERST follow which signal
        .FM_PERST_TIMING_SEL             ( FM_PERST_TIMING_SEL             ),       // choose delay timing parameter
		.iRST_CPU_RESET_R_N              ( RST_CPU0_RESET_R_N              ),
        .oRST_PLD_PCIE_CPU_DEV_PERST_R_N ( RST_PLD_PCIE_CPU0_DCSCM_PERST   )        // To PCIe divices, trigger to reset PCIe devices
    );
   
   //PROCHOT_MEMHOT
   prochot_memhot prochot_memhot_inst
     (
      .iClk(iClk_2M),          
      .iRst_n(iRST_N),          
      
      .iIRQ_CPU0_VRHOT_N(IRQ_CPU0_VRHOT_N_FF),
      .iIRQ_CPU1_VRHOT_N(IRQ_CPU1_VRHOT_N_FF),
      .iIRQ_CPU0_MEM_VRHOT_N(IRQ_CPU0_MEM_VRHOT_N_FF),
      .iIRQ_CPU1_MEM_VRHOT_N(IRQ_CPU1_MEM_VRHOT_N_FF),
      .iSYS_THROTTLE_N(FM_SYS_THROTTLE_R_N),
      
      .oH_CPU0_PROCHOT_LVC1_R_N(H_CPU0_PROCHOT_LVC1_R_N),
      .oH_CPU1_PROCHOT_LVC1_R_N(H_CPU1_PROCHOT_LVC1_R_N),
      .oH_CPU0_MEMHOT_IN_LVC1_R_N(H_CPU0_MEMHOT_IN_LVC1_R_N),
      .oH_CPU1_MEMHOT_IN_LVC1_R_N(H_CPU1_MEMHOT_IN_LVC1_R_N)
      
      );
   
   //SYS_THROTTLE
   sys_throttle sys_throttle_inst
     (
      .iClk(iClk_2M),          
      .iRst_n(iRST_N),          
      
      .iIRQ_PMBUS_PLD_ALERT_N(IRQ_PMBUS_PLD_ALERT_N_FF),
      
      .oFM_SYS_THROTTLE_R_N(FM_SYS_THROTTLE_R_N)
      );
   
   
   //VR BYPASS
   vr_bypass vr_bypass_inst
     (
      .iClk(iClk_2M),                            //clock for sequential logic(), 2MHz 
      .iRst_n(iRST_N && !wBPEna),                //reset signal(), resets state machine to initial state
      
      //FORCE ON JUMPER
      .iFM_FORCE_PWRON_LVC18(iFM_FORCE_PWRON_LVC18),     //VR FORCE ON(), from DBG FPGA thru sGPIO
      
      //CPU PRSNT
      .iFM_CPU0_SKTOCC_LVT3_PLD_N(FM_CPU0_SKTOCC_LVT3_PLD_N_FF),      //SKTOCC_N is used to protect system to not override sequence if CPU is installed
      .iFM_CPU1_SKTOCC_LVT3_PLD_N(FM_CPU1_SKTOCC_LVT3_PLD_N_FF),      //SKTOCC_N is used to protect system to not override sequence if CPU is installed
      .iFM_CPU0_INTR_PRSNT_N(wCpu0IntrPrsnt_n),                  //INTR_PRSNT_N is used to protect system to not override sequence if interposer is installed
      .iFM_CPU1_INTR_PRSNT_N(wCpu1IntrPrsnt_n),                  //INTR_PRSNT_N is used to protect system to not override sequence if interposer is installed
      
      //system power rails PWRGD
      .iPWRGD_P3V3_BP(PWRGD_P3V3_FF),                                 //P3V3 MAIN
      .iPWRGD_PS_PWROK_CPU_PLD_R_BP(PWRGD_PS_PWROK_CPU_PLD_R_FF),     //PS_PWROK
      
      .iPWRGD_P1V0_AUX_BP(iPWRGD_P1V0_AUX),
      .iPWRGD_P1V1_AUX_BP(iPWRGD_P1V1_AUX),
      
      //CPU0 rails PWRGD
      .iPWRGD_PVCCFA_EHV_CPU0_BP(PWRGD_PVCCFA_EHV_CPU0_FF),             //PVCCFA_EHV
      .iPWRGD_PVNN_MAIN_CPU0_BP(PWRGD_PVNN_MAIN_CPU0_FF),               //PVNN
      .iPWRGD_PVCCD0_HV_CPU0_BP(PWRGD_PVCCD0_HV_CPU0_FF),               //PVCCD0
      .iPWRGD_PVCCD1_HV_CPU0_BP(PWRGD_PVCCD1_HV_CPU0_FF),               //PVCCD1
      .iPWRGD_PVCCFA_EHV_FIVRA_CPU0_BP(PWRGD_PVCCFA_EHV_FIVRA_CPU0_FF), //PVCCFA_EHV_FIVRA
      .iPWRGD_PVCCINFAON_CPU0_BP(PWRGD_PVCCINFAON_CPU0_FF),             //PVCCINFAON
      .iPWRGD_PVCCIN_CPU0_BP(PWRGD_PVCCIN_CPU0_FF),                     //PVCCIN
      
      //CPU1 rails PWRGD
      .iPWRGD_PVCCFA_EHV_CPU1_BP(PWRGD_PVCCFA_EHV_CPU1_FF),             //PVCCFA_EHV
      .iPWRGD_PVNN_MAIN_CPU1_BP(PWRGD_PVNN_MAIN_CPU1_FF),               //PVNN
      .iPWRGD_PVCCD0_HV_CPU1_BP(PWRGD_PVCCD0_HV_CPU1_FF),               //PVCCD0
      .iPWRGD_PVCCD1_HV_CPU1_BP(PWRGD_PVCCD1_HV_CPU1_FF),               //PVCCD1
      .iPWRGD_PVCCFA_EHV_FIVRA_CPU1_BP(PWRGD_PVCCFA_EHV_FIVRA_CPU1_FF), //PVCCFA_EHV_FIVRA
      .iPWRGD_PVCCINFAON_CPU1_BP(PWRGD_PVCCINFAON_CPU1_FF),             //PVCCINFAON
      .iPWRGD_PVCCIN_CPU1_BP(PWRGD_PVCCIN_CPU1_FF),                     //PVCCIN
      
      //LED display
      .oLED_STATUS(oLED_STATUS[4:0]),                                   //VR Bypass FSM status to be displayed on LEDs
      
      //System rails Power EN
      .oFM_P3V3_EN_BP(wFM_P3V3_EN_BP),                                  //P3V3 MAIN Enable
      .oFM_PS_EN_R_BP(wFM_PS_EN_R_BP),                                  //PSU Enable
      .oFM_AUX_SW_EN_BP(wFM_AUX_SW_EN_BP),                              //Switch power source from STBY to Main
      .oFM_P5V_EN_BP(wFM_P5V_EN_BP),                                    //Enable P5V main switch, need to be enabled before CPU main rail up
      .oFM_P1V0_AUX_EN_BP(wFM_P1V0_AUX_EN_BP),                          //Enable P1V0 AUX VNN VR
      .oFM_P1V1_AUX_EN_BP(wFM_P1V1_AUX_EN_BP),                          //Enable P1V1 AUX VCCD VR
      
      .oFM_P12V_DIMM_PCIE_SW_CPU0_EN_BP(wFM_P12V_DIMM_PCIE_SW_CPU0_EN_BP),    //Enable PCIE/DIMM 12V Main power switch
      .oFM_P12V_DIMM_PCIE_SW_CPU1_EN_BP(wFM_P12V_DIMM_PCIE_SW_CPU1_EN_BP),    //Enable PCIE/DIMM 12V Main power switch
      
      //CPU0 rails enable
      .oFM_PVCCFA_EHV_CPU0_R_EN_BP(wFM_PVCCFA_EHV_CPU0_R_EN_BP),       //PVCCFA_EHV Enable
      .oFM_PVNN_MAIN_CPU0_R_EN_BP(wFM_PVNN_MAIN_CPU0_R_EN_BP),         //PVNN Enable
      .oFM_PVCCD_HV_CPU0_R_EN_BP(wFM_PVCCD_HV_CPU0_R_EN_BP),           //PVCCD0 Enable

      .oFM_PVCCFA_EHV_FIVRA_CPU0_R_EN_BP(wFM_PVCCFA_EHV_FIVRA_CPU0_R_EN_BP),  //PVCCFA_EHV_FIVRA Enable
      .oFM_PVCCINFAON_CPU0_R_EN_BP(wFM_PVCCINFAON_CPU0_R_EN_BP),       //PVCCINFAON Enable
      .oFM_PVCCIN_CPU0_R_EN_BP(wFM_PVCCIN_CPU0_R_EN_BP),               //PVCCIN Enable
      
      //CPU1 rails enable
      .oFM_PVCC3V3_AUX_CPU1_EN_BP(wFM_PVCC3V3_AUX_CPU1_EN_BP),         //PVCC3P3_AUX Enable, only valid for CPU1
      
      .oFM_PVCCFA_EHV_CPU1_R_EN_BP(wFM_PVCCFA_EHV_CPU1_R_EN_BP),       //PVCCFA_EHV Enable
      .oFM_PVNN_MAIN_CPU1_R_EN_BP(wFM_PVNN_MAIN_CPU1_R_EN_BP),         //PVNN Enable
      .oFM_PVCCD_HV_CPU1_R_EN_BP(wFM_PVCCD_HV_CPU1_R_EN_BP),           //PVCCD0 Enable

      .oFM_PVCCFA_EHV_FIVRA_CPU1_R_EN_BP(wFM_PVCCFA_EHV_FIVRA_CPU1_R_EN_BP),  //PVCCFA_EHV_FIVRA Enable
      .oFM_PVCCINFAON_CPU1_R_EN_BP(wFM_PVCCINFAON_CPU1_R_EN_BP),       //PVCCINFAON Enable
      .oFM_PVCCIN_CPU1_R_EN_BP(wFM_PVCCIN_CPU1_R_EN_BP)               //PVCCIN Enable
      
      
      );

   //---------------------------------------------------------------------------------------------------------------
       // Error detect, convert CATERR and RMCA signals to 2-bit mode signals.
   err_det cpu0_caterr_det_inst(
                                .CATERR_RMCA_N  (wH_CPU0_CATERR_LVC1_N),    
                                .rst_n          (iRST_N),
                                .CLK            (iClk_100M),
                                .MODE           (oH_CPU0_CATERR_LVC1_ENCODE)
                                );
   
   err_det cpu0_rmca_det_inst(
                              .CATERR_RMCA_N  (wH_CPU0_RMCA_LVC1_N),
                              .rst_n          (iRST_N),
                              .CLK            (iClk_100M),
                              .MODE           (oH_CPU0_RMCA_LVC1_ENCODE)
                              );
  
   err_det cpu1_caterr_det_inst(
                                .CATERR_RMCA_N  (wH_CPU1_CATERR_LVC1_N),
                                .rst_n          (iRST_N),
                                .CLK            (iClk_100M),
                                .MODE           (oH_CPU1_CATERR_LVC1_ENCODE)
                                );
  
   err_det cpu1_rmca_det_inst(
                              .CATERR_RMCA_N  (wH_CPU1_RMCA_LVC1_N),
                              .rst_n          (iRST_N),
                              .CLK            (iClk_100M),
                              .MODE           (oH_CPU1_RMCA_LVC1_ENCODE)
                              );
   //---------------------------------------------------------------------------------------------------------------
   
   
   EdgeDetector # //%Parameterizable Edge Detector<br>
     (
      //% Defines Positive Edge (1) or Negative Edge (0)<br>
      .EDGE (0)
      )  CPU0_THERMTRIP_NEGEDGE
       (
        //% Clock Input<br>
        .iClk(iClk_2M),
        //% Asynchronous Reset Input<br>
        .iRst(!iRST_N),
        //% Monitored Input Signal<br>
        .iSignal(wH_CPU0_THERMTRIP_LVC1_N),
        //% Edge Detected Flag<br>
        .oEdgeDetected(wH_CPU0_THERMTRIP_LVC1_N_NEGEDGE)
        );
   
   EdgeDetector # //%Parameterizable Edge Detector<br>
     (
      //% Defines Positive Edge (1) or Negative Edge (0)<br>
      .EDGE (0)
      )  CPU1_THERMTRIP_NEGEDGE
       (
        //% Clock Input<br>
        .iClk(iClk_2M),
        //% Asynchronous Reset Input<br>
        .iRst(!iRST_N),
        //% Monitored Input Signal<br>
        .iSignal(wH_CPU1_THERMTRIP_LVC1_N),
        //% Edge Detected Flag<br>
        .oEdgeDetected(wH_CPU1_THERMTRIP_LVC1_N_NEGEDGE)
        );
		
			EdgeDetector # //%Parameterizable Edge Detector<br>
(
                //% Defines Positive Edge (1) or Negative Edge (0)<br>
    .EDGE (0)
)  CPU0_MEMTRIP_NEGEDGE
(
            //% Clock Input<br>
    .iClk(iClk_2M),
            //% Asynchronous Reset Input<br>
    .iRst(!iRST_N),
            //% Monitored Input Signal<br>
    .iSignal(wH_CPU0_MEMTRIP_LVC1_N),
            //% Edge Detected Flag<br>
    .oEdgeDetected(wH_CPU0_MEMTRIP_LVC1_N_NEGEDGE)
);

	EdgeDetector # //%Parameterizable Edge Detector<br>
(
                //% Defines Positive Edge (1) or Negative Edge (0)<br>
    .EDGE (0)
)  CPU1_MEMTRIP_NEGEDGE
(
            //% Clock Input<br>
    .iClk(iClk_2M),
            //% Asynchronous Reset Input<br>
    .iRst(!iRST_N),
            //% Monitored Input Signal<br>
    .iSignal(wH_CPU1_MEMTRIP_LVC1_N),
            //% Edge Detected Flag<br>
    .oEdgeDetected(wH_CPU1_MEMTRIP_LVC1_N_NEGEDGE)
);

    EdgeDetector # //%Parameterizable Edge Detector<br>
(
                //% Defines Positive Edge (1) or Negative Edge (0)<br>
    .EDGE (0)
)  PFR_AUX_PWRGD_NEGEDGE
(
            //% Clock Input<br>
    .iClk(iClk_2M),
            //% Asynchronous Reset Input<br>
    .iRst(!iRST_N),
            //% Monitored Input Signal<br>
    .iSignal(wAUX_PWRGD_CPU0_SCM),
            //% Edge Detected Flag<br>
    .oEdgeDetected(wAUX_PWRGD_CPU0_SCM_NEGEDEG)
);

    EdgeDetector #(
        .EDGE (0)       // 1'b0 for negative edge detection
    ) AUX_PWRGD_NEGEDGE (
        .iClk           ( iClk_2M                          ),
        .iRst           ( !iRST_N                          ),
        .iSignal        ( PWRGD_AUX_PWRGD_CPU0_PLD         ),
        .oEdgeDetected  ( PWRGD_AUX_PWRGD_CPU0_PLD_NEGEDGE )
    );

    EdgeDetector #(
        .EDGE (1)       // 1'b1 for positive edge detection
    ) AUX_PWRGD_POSEDGE (
        .iClk           ( iClk_2M                          ),
        .iRst           ( !iRST_N                          ),
        .iSignal        ( PWRGD_AUX_PWRGD_CPU0_PLD         ),
        .oEdgeDetected  ( PWRGD_AUX_PWRGD_CPU0_PLD_POSEDGE )
    );
   
   assign oLED_STATUS[7:5]                = 3'b0;    //Turn off unused STATUS LED
   
   assign wCPU0_DIMM_FAULT                 = oCPU0_DIMM_FLT_CODE && 6'b111111;
   assign wCPU1_DIMM_FAULT                 = oCPU1_DIMM_FLT_CODE && 6'b111111;
   assign wCPU_PWR_FLT                     = (wCPU0_MEM_PWR_FLT && FM_CPU1_SKTOCC_LVT3_PLD_N_FF) || (!FM_CPU1_SKTOCC_LVT3_PLD_N_FF && (wCPU0_MEM_PWR_FLT || wCPU1_MEM_PWR_FLT));
   
   //------------------------------------------------------------------------------------------------
   //PostCode Error Code Assignment
   assign oCPU0_FLT_CODE = {1'b0,wCPU0_PWR_FLT_PVCCIN,wCPU0_PWR_FLT_PVCCD0_HV,wCPU0_PWR_FLT_PVNN,wCPU0_PWR_FLT_PVCCINFAON_CPU,wCPU0_PWR_FLT_EHV_FIVRA_CPU,wCPU0_PWR_FLT_EHV_CPU};
   assign oCPU1_FLT_CODE = {1'b0,wCPU1_PWR_FLT_PVCCIN,wCPU1_PWR_FLT_PVCCD0_HV,wCPU1_PWR_FLT_PVNN,wCPU1_PWR_FLT_PVCCINFAON_CPU,wCPU1_PWR_FLT_EHV_FIVRA_CPU,wCPU1_PWR_FLT_EHV_CPU};
   
   //Combinational logic
   assign PWRGD_CPU0_LVC1_R       =  wPWRGD_CPU0_LVC1_R;              //this is PWRGD out from CPU FPGA to CPU
   assign oPWRGD_CPU0_LVC1_R      =  wPWRGD_CPU0_LVC1_R;              //this is PWRGD out from CPU FPGA to LVDS
   
   
   assign oMEM_PWR_FLT             =  wMEM0_PWR_FLT | wMEM1_PWR_FLT;
   assign oCPU_PWR_FLT             =  wCPU0_MEM_PWR_FLT | wCPU1_MEM_PWR_FLT;  //
   assign wVR_PWROFF_ERR           =  wVR_PWROFF_CPU0_ERR | wVR_PWROFF_CPU1_ERR;
   assign wAUX_VR_PWROFF_ERR       =  wAUX_VR_PWROFF_CPU0_ERR | wAUX_VR_PWROFF_CPU1_ERR;
   
   //Gating THERMTRIP untill CPU out of RESET
   assign wH_CPU0_THERMTRIP_LVC1_N =  RST_CPU0_RESET_R_N ? H_CPU0_THERMTRIP_LVC1_N_FF : 1'b1;
   assign wH_CPU1_THERMTRIP_LVC1_N =  RST_CPU1_RESET_R_N ? H_CPU1_THERMTRIP_LVC1_N_FF : 1'b1;
   assign wH_CPU_THERMTRIP_LVC1_N  =  wH_CPU0_THERMTRIP_LVC1_N && wH_CPU1_THERMTRIP_LVC1_N;

   assign     wH_CPU0_MEMTRIP_LVC1_N   =  RST_CPU0_RESET_R_N ? oH_CPU0_MEMTRIP_LVC1_N : 1'b1;
   assign     wH_CPU1_MEMTRIP_LVC1_N   =  (!FM_CPU1_SKTOCC_LVT3_PLD_N_FF && RST_CPU1_RESET_R_N) ? oH_CPU1_MEMTRIP_LVC1_N : 1'b1;
   assign     wH_CPU_MEMTRIP_LVC1_N   =  wH_CPU0_MEMTRIP_LVC1_N && wH_CPU1_MEMTRIP_LVC1_N;
   
   //Latch THERMTRIP for BMC
   assign oH_CPU0_THERMTRIP_LVC1_N =  rH_CPU0_THERMTRIP_LVC1_N_LATCHED;
   assign oH_CPU1_THERMTRIP_LVC1_N =  rH_CPU1_THERMTRIP_LVC1_N_LATCHED;
   
   assign oFM_THERMTRIP_CPU0_LED_LATCHED = !(rH_CPU0_THERMTRIP_LVC1_N_LATCHED && rH_CPU0_MEMTRIP_LVC1_N_LATCHED) ? HIGH : LOW; // If CPU0 THERMTRIP/MEMTRIP, output long 1'b1;
   assign oFM_THERMTRIP_CPU1_LED_LATCHED = !(rH_CPU1_THERMTRIP_LVC1_N_LATCHED && rH_CPU1_MEMTRIP_LVC1_N_LATCHED) ? HIGH : LOW; // If CPU1 THERMTRIP/MEMTRIP, output long 1'b1;
   assign oHeartBeat = wHeartBeat;   
   
   always @(posedge iClk_2M or negedge iRST_N) 
     begin
        if(!iRST_N)
          begin
             rH_CPU0_THERMTRIP_LVC1_N_LATCHED   <=  HIGH;
          end
        else 
          begin
             if(wH_CPU0_THERMTRIP_LVC1_N_NEGEDGE) begin
                rH_CPU0_THERMTRIP_LVC1_N_LATCHED  <=  LOW;
             end
          end
     end // always @ (posedge iClk_2M or negedge iRST_N)
   
   always @(posedge iClk_2M or negedge iRST_N)
     begin
        if(!iRST_N)
          begin
             rH_CPU1_THERMTRIP_LVC1_N_LATCHED   <=  HIGH;
          end
        else 
          begin
             if(wH_CPU1_THERMTRIP_LVC1_N_NEGEDGE) begin
                rH_CPU1_THERMTRIP_LVC1_N_LATCHED  <=  LOW;
             end
          end
     end // always @ (posedge iClk_2M or negedge iRST_N)
	 
    always @ (posedge iClk_2M or negedge iRST_N) begin
        if (!iRST_N) begin
            rH_CPU0_MEMTRIP_LVC1_N_LATCHED          <=  HIGH;
        end
        else begin
            if (wH_CPU0_MEMTRIP_LVC1_N_NEGEDGE) begin
                rH_CPU0_MEMTRIP_LVC1_N_LATCHED      <=  LOW;
            end
        end
    end

    always @ (posedge iClk_2M or negedge iRST_N) begin
        if (!iRST_N) begin
            rH_CPU1_MEMTRIP_LVC1_N_LATCHED          <=  HIGH;
        end
        else begin
            if (wH_CPU1_MEMTRIP_LVC1_N_NEGEDGE) begin
                rH_CPU1_MEMTRIP_LVC1_N_LATCHED      <=  LOW;
            end
        end
    end

    always @ (posedge iClk_2M or negedge iRST_N) begin
        if (!iRST_N) begin
            rAUX_PWRGD_CPU0_SCM_NEGEDEG_LATCHED         <=  LOW;
        end
        else begin
            if (wAUX_PWRGD_CPU0_SCM_NEGEDEG) begin
                rAUX_PWRGD_CPU0_SCM_NEGEDEG_LATCHED     <=  HIGH;    // If detected GPO_1_PFR_CPU0_PLT_AUX_PWRGD de-assertion, latch this to gate S5_PWR_RETAINED
			end else if ((PWRGD_AUX_PWRGD_CPU0_PLD_NEGEDGE || PWRGD_AUX_PWRGD_CPU0_PLD_POSEDGE) && wAUX_PWRGD_CPU0_SCM) begin
				rAUX_PWRGD_CPU0_SCM_NEGEDEG_LATCHED     <=  LOW;     // If detected GPO_1_PFR_CPU0_PLT_AUX_PWRGD asserted again in next transition of AUX_PWRGD, clear this latch to recover S5_PWR_RETAINED
			end
        end
    end
	
   //------------------------------------------------------------------------------------------------
   //Signals to LVDS/SGPIO also used by internal logic 
   //------------------------------------------------------------------------------------------------
   assign  oFM_CPU1_SKTOCC_LVT3_PLD_N  =  FM_CPU1_SKTOCC_LVT3_PLD_N_FF;       //to SCM FPGA thru LVDS
   assign  oFM_CPU0_SKTOCC_LVT3_PLD_N  =  FM_CPU0_SKTOCC_LVT3_PLD_N_FF;       //to SCM FPGA thru LVDS
   assign  oFM_CPU0_PROC_ID1           =  FM_CPU0_PROC_ID1_FF;                //to SCM FPGA thru LVDS
   assign  oFM_CPU0_PROC_ID0           =  FM_CPU0_PROC_ID0_FF;                //to SCM FPGA thru LVDS
   assign  oFM_CPU1_PROC_ID1           =  FM_CPU1_PROC_ID1_FF;                //to SCM FPGA thru LVDS
   assign  oFM_CPU1_PROC_ID0           =  FM_CPU1_PROC_ID0_FF;                //to SCM FPGA thru LVDS
   assign  oFM_CPU0_PKGID2             =  FM_CPU0_PKGID2_FF;                  //to SCM FPGA thru LVDS
   assign  oFM_CPU0_PKGID1             =  FM_CPU0_PKGID1_FF;                  //to SCM FPGA thru LVDS
   assign  oFM_CPU0_PKGID0             =  FM_CPU0_PKGID0_FF;                  //to SCM FPGA thru LVDS
   assign  oFM_CPU1_PKGID2             =  FM_CPU1_PKGID2_FF;                  //to SCM FPGA thru LVDS
   assign  oFM_CPU1_PKGID1             =  FM_CPU1_PKGID1_FF;                  //to SCM FPGA thru LVDS
   assign  oFM_CPU1_PKGID0             =  FM_CPU1_PKGID0_FF;                  //to SCM FPGA thru LVDS
   assign  oPWRGD_PS_PWROK_CPU_PLD_R   =  PWRGD_PS_PWROK_CPU_PLD_R_FF;        //to SCM FPGA thru LVDS  
   assign  oFM_SLPS4_CPU0_CPU_PLD_N    =  FM_SLPS4_CPU0_CPU_PLD_N_FF;         //to SCM FPGA thru LVDS  
   assign  oFM_SLPS3_CPU0_CPU_PLD_N    =  FM_SLPS3_CPU0_CPU_PLD_N_FF;         //to SCM FPGA thru LVDS  
   assign  oFM_SLPS4_CPU1_CPU_PLD_N    =  FM_SLPS4_CPU1_CPU_PLD_N_FF;         //to SCM FPGA thru LVDS  
   assign  oFM_SLPS3_CPU1_CPU_PLD_N    =  FM_SLPS4_CPU1_CPU_PLD_N_FF;         //to SCM FPGA thru LVDS  
   assign  oIRQ_PMBUS_PLD_ALERT_N      =  IRQ_PMBUS_PLD_ALERT_N_FF;           //to SCM FPGA thru LVDS  
   assign  oIRQ_CPU0_VRHOT_N           =  IRQ_CPU0_VRHOT_N_FF;                //to SCM FPGA thru LVDS
   assign  oIRQ_CPU1_VRHOT_N           =  IRQ_CPU1_VRHOT_N_FF;                //to SCM FPGA thru LVDS
   assign  oIRQ_CPU0_MEM_VRHOT_N       =  IRQ_CPU0_MEM_VRHOT_N_FF;            //to SCM FPGA thru LVDS
   assign  oIRQ_CPU1_MEM_VRHOT_N       =  IRQ_CPU1_MEM_VRHOT_N_FF;            //to SCM FPGA thru LVDS  
   assign  oFM_POSTCODE_PFR_CC_SEL_N   =  FM_POSTCODE_PFR_CC_SEL_N_FF;        //to DBG FOGA thru sGPIO
   

    
    //Expansion card PWRDIS
    pca9555 #(.DEVICE_ADDR(7'h2F),
	          .CC_FREQM(50))
    cpu0_exp_PWRDIS (
        .iClk        (iClk_50M),
        .iRst_n      (iRST_N),
        .iSCL        (SMB_PCIE_STBY_LVC3_SCL),
        .ioSDA       (SMB_PCIE_STBY_LVC3_SDA),
        .ioDataP0    ({
                      FM_PWRDIS_EDSFF,    //bit 7   output
                      wUnusedP1      //bit 0~6   output
                      }),
        .ioDataP1    (),         //port1 not in use
        .oSmbAlert_n ()
        );
   
    
    //Expansion card
	
	wire wSTG_MNGMT_ENC_LOCATE, wSTG_MNGMT_ENC_FAULT; //New order in Bits for Expantion Card
	
    pca9555 #(.DEVICE_ADDR(7'h20),
	          .CC_FREQM(50))
    cpu0_exp (
        .iClk        (iClk_50M),
        .iRst_n      (iRST_N),
        .iSCL        (SMB_PEHPCPU0_LVC3_FPGA_SCL),
        .ioSDA       (SMB_PEHPCPU0_LVC3_FPGA_SDA),
        .ioDataP0    ({
		                wUnusedP2[3],                   //bit 7
                        wUnusedP2[2],                   //bit 6
                        FM_SFFX4_EXPCARD_IO_B_0,        //bit 5
                        FM_M2_EDSFF_PRSNT_N,            //bit 4
                        wUnusedP2[1],                   //bit 3
                        wUnusedP2[0],                   //bit 2
                        wSTG_MNGMT_ENC_LOCATE,          //bit 1
                        wSTG_MNGMT_ENC_FAULT            //bit 0

                       }),
        .ioDataP1     (),         //port1 not in use
        .oSmbAlert_n  ()
    );
	
	hp_led_ctrl led_ctrl
    (
     .iClk      ( iClk_2M                       ),
     .iRst_n    ( iRST_N                        ),
     .iEna_n    ( 1'b0                          ),            
     .iLocate   ( wSTG_MNGMT_ENC_LOCATE         ),
     .iFault    ( wSTG_MNGMT_ENC_FAULT          ),
     .oAmberLed ( FM_FAULT_LED_AMBER_M2_EDSFF_N )
     );
   
   ClkDivTree ClkDivTree_U
     (
      .i_Clk(iClk_2M),
      .i_Rst_n(iRST_N),
      .o_1uSCE(w_1uSCE),
      .o_5uSCE(w_5uSCE),
      .o_10uSCE(w_10uSCE),
      .o_50uSCE(w_50uSCE),
      .o_500uSCE(w_500uSCE),
      .o_1mSCE(w_1mSCE),
      .o_20mSCE(w_20mSCE),  
      .o_250mSCE(w_250mSCE),
      .o_1SCE(w_1SCE)
      );
   
   
   //------------------------------------------------------------------------------------------------
   Ocp_ctrl Ocp_ctl_U0
     (
      .iClk(iClk_2M),
      .iRst_n(iRST_N),
      .i_1mSCE(w_1mSCE),
      .i_20mSCE(w_20mSCE),
      
      .i_OCP_CARD_PRSNTB_N(FM_OCP0_CARD_PRSNTB_LVC3_N_FF),
      .iPSU_PWR_OK(PWRGD_PS_PWROK_CPU_PLD_R_FF),
      .i_PWRGD_NIC_PWR(PWRGD_OCP0_PWR_FF),
      
      .o_FM_OCP_AUX_PWR_EN(o_FM_OCP_AUX_PWR_EN),
      .o_FM_OCP_MAIN_PWR_EN(o_FM_OCP_MAIN_PWR_EN),
      .o_FM_PLD_OCP_RBT_ISOLATE_N(o_FM_PLD_OCP_RBT_ISOLATE_N),
      .o_PWRGD_NIC_PWR_DLY(w_PWRGD_OCP0_PWR_DLY),
      .o_OcpPwrFlt_LED(o_OcpPwrFlt_LED)
      
      );
   
   HeartBeat HeartBeat250mSec
     (
      .iClk(iClk_2M),
      .iRst_n(iRST_N),
      .oHeartBeat(wHeartBeat)
      );
   
   
   DbgBP dbg1 (
               .source
               ({
                 wBPEna,
                 wBPGo,                                                   //[26]
                 wPvcc3v3AuxCpu1,                                         //[25]
                 wP1v0MaxEna,wP1v1MaxEna,                                 //[24],[23]
                 wPvccfaEhvCpu0Ena, wPvccfaEhvCpu1Ena,                    //[22],[21]
                 wPvnnAuxCpu0Ena,wPvnnAuxCpu1Ena,                         //[20],[19]
                 wPsuEna,wAuxSwEna,                                       //[18],[17]
                 wP12VDimmPcieSwCpu0Ena,wP12VDimmPcieSwCpu1Ena,           //[16],[15]
                 wPldClksDevEna,wFmP3V3En,                                //[14],[13]
                 wPVccd0HvCpu0Ena,wPVccd1HvCpu0Ena,                       //[12],[11]
                 wPVccd0HvCpu1Ena,wPVccd1HvCpu1Ena,                       //[10],[9]
                 wPvccfaEhvFivraCpu0Ena,wPvccfaEhvFivraCpu1Ena,           //[8],[6]
                 wPvccInfaOnCpu0Ena,wPvccInfaOnCpu1Ena,                   //[6],[5]
                 wPvccinCpu0Ena,wPvccinCpu1Ena,                           //[4],[3]
                 wFmTs3ds10224EnaOD,                                      //[2]
                 wFmTs3ds10224EnbOD,                                      //[1]
                 WFmP5VEna                                                //[0]
                 }),                //28 sources
               .probe
               ({
                 FM_PVCCFA_EHV_CPU0_R_EN,
                 FM_PVNN_MAIN_CPU0_R_EN,
                 FM_PVCCD_HV_CPU0_R_EN,
                 FM_PVCCD_HV_CPU1_R_EN,
                 iFM_FORCE_PWRON_LVC18
                 }),
               .source_clk(iClk_2M)
               );
   
   
   assign FM_P3V3_EN                    = wBPEna ? (wFmP3V3En                && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_P3V3_EN_BP                    : wFM_P3V3_EN );
   assign FM_PS_EN_R                    = wBPEna ? (wPsuEna                  && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PS_EN_R_BP                    : wFM_PS_EN_R );
   assign FM_AUX_SW_EN                  = wBPEna ? (wAuxSwEna                && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_AUX_SW_EN_BP                  : wFM_AUX_SW_EN ); 
   
   assign FM_P1V0_AUX_EN                = wBPEna ? (wP1v0MaxEna              && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_P1V0_AUX_EN_BP                : wFM_P1V0_AUX_EN );
   assign FM_P1V1_AUX_EN                = wBPEna ? (wP1v1MaxEna              && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_P1V1_AUX_EN_BP                : wFM_P1V1_AUX_EN );
   
   assign FM_P12V_DIMM_PCIE_SW_CPU0_EN  = wBPEna ? (wP12VDimmPcieSwCpu0Ena   && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_P12V_DIMM_PCIE_SW_CPU0_EN_BP  : wFM_P12V_DIMM_PCIE_SW_CPU0_EN );
   assign FM_P12V_DIMM_PCIE_SW_CPU1_EN  = wBPEna ? (wP12VDimmPcieSwCpu1Ena   && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_P12V_DIMM_PCIE_SW_CPU1_EN_BP  : wFM_P12V_DIMM_PCIE_SW_CPU1_EN );
   
   assign FM_PVCCFA_EHV_CPU0_R_EN       = wBPEna ? (wPvccfaEhvCpu0Ena        && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCFA_EHV_CPU0_R_EN_BP       : wFM_PVCCFA_EHV_CPU0_R_EN );
   assign FM_PVNN_MAIN_CPU0_R_EN        = wBPEna ? (wPvnnAuxCpu0Ena          && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVNN_MAIN_CPU0_R_EN_BP        : wFM_PVNN_MAIN_CPU0_R_EN );
   assign FM_PVCCD_HV_CPU0_R_EN         = wBPEna ? (wPVccd0HvCpu0Ena         && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCD_HV_CPU0_R_EN_BP         : wFM_PVCCD_HV_CPU0_R_EN );
   assign FM_PVCCFA_EHV_FIVRA_CPU0_R_EN = wBPEna ? (wPvccfaEhvFivraCpu0Ena   && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCFA_EHV_FIVRA_CPU0_R_EN_BP : wFM_PVCCFA_EHV_FIVRA_CPU0_R_EN );
   assign FM_PVCCINFAON_CPU0_R_EN       = wBPEna ? (wPvccInfaOnCpu0Ena       && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCINFAON_CPU0_R_EN_BP       : wFM_PVCCINFAON_CPU0_R_EN );
   assign FM_PVCCIN_CPU0_R_EN           = wBPEna ? (wPvccinCpu0Ena           && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCIN_CPU0_R_EN_BP           : wFM_PVCCIN_CPU0_R_EN );
   
   assign FM_PVCC3V3_AUX_CPU1_EN        = wBPEna ? (wPvcc3v3AuxCpu1          && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCC3V3_AUX_CPU1_EN_BP        : wFM_PVCC3V3_AUX_CPU1_EN );
   
   assign FM_PVCCFA_EHV_CPU1_R_EN       = wBPEna ? (wPvccfaEhvCpu1Ena        && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCFA_EHV_CPU1_R_EN_BP       : wFM_PVCCFA_EHV_CPU1_R_EN );
   assign FM_PVNN_MAIN_CPU1_R_EN        = wBPEna ? (wPvnnAuxCpu1Ena          && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVNN_MAIN_CPU1_R_EN_BP        : wFM_PVNN_MAIN_CPU1_R_EN );
   assign FM_PVCCD_HV_CPU1_R_EN         = wBPEna ? (wPVccd0HvCpu1Ena         && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCD_HV_CPU1_R_EN_BP         : wFM_PVCCD_HV_CPU1_R_EN );
   assign FM_PVCCFA_EHV_FIVRA_CPU1_R_EN = wBPEna ? (wPvccfaEhvFivraCpu1Ena   && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCFA_EHV_FIVRA_CPU1_R_EN_BP : wFM_PVCCFA_EHV_FIVRA_CPU1_R_EN );
   assign FM_PVCCINFAON_CPU1_R_EN       = wBPEna ? (wPvccInfaOnCpu1Ena       && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCINFAON_CPU1_R_EN_BP       : wFM_PVCCINFAON_CPU1_R_EN );
   assign FM_PVCCIN_CPU1_R_EN           = wBPEna ? (wPvccinCpu1Ena           && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_PVCCIN_CPU1_R_EN_BP           : wFM_PVCCIN_CPU1_R_EN );
   assign FM_P5V_EN                     = wBPEna ? (WFmP5VEna                && wBPGo)  : ( iFM_FORCE_PWRON_LVC18 ? wFM_P5V_EN_BP                     : wFM_P5V_EN );
   
   
   
endmodule
